Datasheet > IDT71V3576200PF

IDT71V3576200PF

更新时间： 2024-11-15 07:47:39

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
17页	294K
描述
Standard SRAM, 128KX36, 3.1ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100

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IDT71V3576200PF 数据手册

128K X 36, 256K X 18, 3.3V

SYNCHRONOUS SRAMS WITH

2.5V I/O OPTION, PIPELINED OUTPUTS,

BURST COUNTER,

PRELIMINARY

IDT71V2576

IDT71V2578

IDT71V3576

IDT71V3578

SINGLE CYCLE DESELECT

DESCRIPTION:

FEATURES:

The IDT71Vx576/578 are high-speed SRAMs organized as 128K x 36/

256K x 18. The IDT71Vx576/578 SRAMs contain write, data, address and

controlregisters. InternallogicallowstheSRAMtogenerateaself-timedwrite

basedupona decisionwhichcanbe leftuntilthe endofthe write cycle.

Theburstmodefeatureoffersthehighestlevelofperformancetothesystem

designer,astheIDT71Vx576/578canprovidefourcyclesofdataforasingle

addresspresentedtotheSRAM. Aninternalburstaddresscounteracceptsthe

firstcycleaddressfromtheprocessor,initiatingtheaccesssequence.Thefirst

cycleofoutputdatawillbepipelinedforonecyclebeforeitisavailableonthe

next rising clock edge. If burst mode operation is selected (ADV=LOW),

the subsequent three cycles of output data will be available to the user on

the next three rising clock edges. The order of these three addresses are

defined by the internal burst counter and the LBO input pin.

• 128K x 36, 256K x 18 memory configurations

• Supports high system speed:

– 200MHz 3.1ns clock access time

– 183MHz 3.3ns clock access time

– 166MHz 3.5ns clock access time

– 150MHz 3.8ns clock access time

– 133MHz 4.2ns clock access time

• LBO input selects interleaved or linear burst mode

• Self-timed write cycle with global write control (GW), byte write

enable (BWE), and byte writes (BWx)

• 3.3V core power supply

• Power down controlled by ZZ input

• 2.5V or 3.3V I/O option

TheIDT71Vx576/578SRAMsutilizeIDT’slatesthigh-performanceCMOS

processandarepackagedinaJEDECstandard14mmx20mm100-leadthin

plastic quad flatpack (TQFP) as well as a 119-lead ball grid array (BGA).

• Packaged in a JEDEC Standard 100-lead plastic thin quad flatpack

(TQFP) and 119-lead ball grid array (BGA)

PIN DESCRIPTION SUMMARY

-A17

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

0, CS

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

BWE

BW , BW

(1)

, BW

CLK

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Synchronous

ADV

ADSC

ADSP

LBO

Asynchronous

Synchronous

N/A

I/O

-I/O31, I/OP1-I/OP4

DD, VDDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

N/A

4876 tbl 01

NOTE:

1. BW3 and BW4 are not applicable for the IDT71Vx578.

APRIL 1999

1998 Integrated Device Technology, Inc.

DSC-4876/2

12 3 4 5 6 7...17

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与IDT71V3576200PF相关器件

型号	品牌	获取价格	描述	数据表
IDT71V3576S	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V3576S133BG	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V3576S133BG8	IDT	获取价格	Cache SRAM, 128KX36, 4.2ns, CMOS, PBGA119, BGA-119
IDT71V3576S133BGG	IDT	获取价格	Cache SRAM, 128KX36, 4.2ns, CMOS, PBGA119, ROHS COMPLIANT, BGA-119
IDT71V3576S133BGG8	IDT	获取价格	Cache SRAM, 128KX36, 4.2ns, CMOS, PBGA119, BGA-119
IDT71V3576S133BGGI	IDT	获取价格	Cache SRAM, 128KX36, 4.2ns, CMOS, PBGA119, ROHS COMPLIANT, BGA-119
IDT71V3576S133BGGI8	IDT	获取价格	Cache SRAM, 128KX36, 4.2ns, CMOS, PBGA119, BGA-119
IDT71V3576S133BGI	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V3576S133BGI8	IDT	获取价格	Cache SRAM, 128KX36, 4.2ns, CMOS, PBGA119, BGA-119
IDT71V3576S133BQ	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin

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