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IDT71V30S25TF8 PDF预览

IDT71V30S25TF8

更新时间: 2024-11-04 19:42:19
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
14页 117K
描述
Dual-Port SRAM, 1KX8, 25ns, CMOS, PQFP64, STQFP-64

IDT71V30S25TF8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:STQFP-64针数:64
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.82
最长访问时间:25 nsI/O 类型:COMMON
JESD-30 代码:S-PQFP-G64JESD-609代码:e0
长度:10 mm内存密度:8192 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端口数量:2端子数量:64
字数:1024 words字数代码:1000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:1KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP64,.47SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.005 A
最小待机电流:3 V子类别:SRAMs
最大压摆率:0.15 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:10 mmBase Number Matches:1

IDT71V30S25TF8 数据手册

 浏览型号IDT71V30S25TF8的Datasheet PDF文件第2页浏览型号IDT71V30S25TF8的Datasheet PDF文件第3页浏览型号IDT71V30S25TF8的Datasheet PDF文件第4页浏览型号IDT71V30S25TF8的Datasheet PDF文件第5页浏览型号IDT71V30S25TF8的Datasheet PDF文件第6页浏览型号IDT71V30S25TF8的Datasheet PDF文件第7页 
IDT71V30S/L  
HIGH-SPEED 3.3V  
1K X 8 DUAL-PORT  
STATIC RAM  
Features  
High-speed access  
On-chip port arbitration logic  
Interrupt flags for port-to-port communication  
– Commercial: 25/35/55ns (max.)  
Low-power operation  
IDT71V30S  
Active: 375mW (typ.)  
Standby: 5mW (typ.)  
IDT71V30L  
Fully asynchronous operation from either port  
Battery backup operation, 2V data retention (L Only)  
TTL-compatible, single 3.3V ±0.3V power supply  
Industrial temperature range (-40OC to +85OC) is available  
for selected speeds  
Active: 375mW (typ.)  
Standby: 1mW (typ.)  
Functional Block Diagram  
OER  
OEL  
CER  
R/WR  
CEL  
R/WL  
I/O0R-I/O7R  
I/O0L- I/O7L  
I/O  
Control  
I/O  
Control  
(1)  
BUSYL  
(1)  
BUSYR  
A9L  
A9R  
Address  
MEMORY  
ARRAY  
Address  
Decoder  
Decoder  
A0L  
A0R  
10  
10  
ARBITRATION  
and  
INTERRUPT  
LOGIC  
CEL  
OEL  
CER  
OER  
R/WR  
R/WL  
(2)  
INTL  
(2)  
INTR  
3741 drw 01  
NOTES:  
1. IDT71V30: BUSY outputs are non-tristatable push-pulls.  
2. INT outputs are non-tristable push-pull output structure.  
JANUARY 2001  
1
DSC 3741/7  
©2000IntegratedDeviceTechnology,Inc.  

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