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IDT71V124S15 PDF预览

IDT71V124S15

更新时间: 2024-11-11 22:34:27
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
8页 67K
描述
3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Revolutionary Pinout

IDT71V124S15 数据手册

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3.3V CMOS Static RAM  
1 Meg (128K x 8-Bit)  
Revolutionary Pinout  
IDT71V124  
Features  
Description  
128K x 8 advanced high-speed CMOS static RAM  
JEDEC revolutionary pinout (center power/GND) for  
reduced noise  
The IDT71V124 is a 1,048,576-bit high-speed static RAM orga-  
nized as 128K x 8. It is fabricated using IDTs high-performance, high-  
reliability CMOS technology. This state-of-the-art technology, com-  
bined with innovative circuit design techniques, provides a cost-  
effective solution for high-speed memory needs. The JEDEC center  
power/GND pinout reduces noise generation and improves system  
performance.  
Commercial (0°C to +70°C) and Industrial (–40°C to  
+85°C) temperature options  
Equal access and cycle times  
Industrial and Commercial: 15/20ns  
One Chip Select plus one Output Enable pin  
Bidirectional inputs and outputs directly  
LVTTL-compatible  
Low power consumption via chip deselect  
Available in 32-pin 400 mil Plastic SOJ.  
TheIDT71V124has anoutputenablepinwhichoperates as fastas  
7ns, with address access times as fast as 15ns available. All bidirec-  
tionalinputs andoutputs oftheIDT71V124areLVTTL-compatibleand  
operation is from a single 3.3V supply. Fully static asynchronous  
circuitry is used; no clocks or refreshes are required for operation.  
The IDT71V124 is packaged in 32-pin 400 mil Plastic SOJ.  
Functional Block Diagram  
A0  
1,048,576-BIT  
MEMORY ARRAY  
ADDRESS  
DECODER  
A16  
8
8
I/O0 - I/O7  
I/O CONTROL  
8
WE  
OE  
CS  
CONTROL  
LOGIC  
3484 drw 01  
AUGUST 2000  
1
©2000IntegratedDeviceTechnology,Inc.  
DSC-3484/05  

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3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Revolutionary Pinout