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IDT71V124S20Y PDF预览

IDT71V124S20Y

更新时间: 2024-09-27 22:34:27
品牌 Logo 应用领域
艾迪悌 - IDT 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
8页 67K
描述
3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Revolutionary Pinout

IDT71V124S20Y 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOJ包装说明:0.400 INCH, PLASTIC, SOJ-32
针数:32Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.57Is Samacsys:N
最长访问时间:20 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-J32JESD-609代码:e0
长度:20.955 mm内存密度:1048576 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端口数量:1端子数量:32
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX8
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ32,.44封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
电源:3.3 V认证状态:Not Qualified
座面最大高度:3.683 mm最大待机电流:0.005 A
最小待机电流:3 V子类别:SRAMs
最大压摆率:0.095 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:J BEND端子节距:1.27 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

IDT71V124S20Y 数据手册

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3.3V CMOS Static RAM  
1 Meg (128K x 8-Bit)  
Revolutionary Pinout  
IDT71V124  
Features  
Description  
128K x 8 advanced high-speed CMOS static RAM  
JEDEC revolutionary pinout (center power/GND) for  
reduced noise  
The IDT71V124 is a 1,048,576-bit high-speed static RAM orga-  
nized as 128K x 8. It is fabricated using IDTs high-performance, high-  
reliability CMOS technology. This state-of-the-art technology, com-  
bined with innovative circuit design techniques, provides a cost-  
effective solution for high-speed memory needs. The JEDEC center  
power/GND pinout reduces noise generation and improves system  
performance.  
Commercial (0°C to +70°C) and Industrial (–40°C to  
+85°C) temperature options  
Equal access and cycle times  
Industrial and Commercial: 15/20ns  
One Chip Select plus one Output Enable pin  
Bidirectional inputs and outputs directly  
LVTTL-compatible  
Low power consumption via chip deselect  
Available in 32-pin 400 mil Plastic SOJ.  
TheIDT71V124has anoutputenablepinwhichoperates as fastas  
7ns, with address access times as fast as 15ns available. All bidirec-  
tionalinputs andoutputs oftheIDT71V124areLVTTL-compatibleand  
operation is from a single 3.3V supply. Fully static asynchronous  
circuitry is used; no clocks or refreshes are required for operation.  
The IDT71V124 is packaged in 32-pin 400 mil Plastic SOJ.  
Functional Block Diagram  
A0  
1,048,576-BIT  
MEMORY ARRAY  
ADDRESS  
DECODER  
A16  
8
8
I/O0 - I/O7  
I/O CONTROL  
8
WE  
OE  
CS  
CONTROL  
LOGIC  
3484 drw 01  
AUGUST 2000  
1
©2000IntegratedDeviceTechnology,Inc.  
DSC-3484/05  

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IDT71V124SA10PHI IDT

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3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout