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IDT7143LA35J PDF预览

IDT7143LA35J

更新时间: 2024-11-25 23:01:11
品牌 Logo 应用领域
艾迪悌 - IDT 存储内存集成电路静态存储器
页数 文件大小 规格书
16页 141K
描述
HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS

IDT7143LA35J 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:LCC
包装说明:QCCJ, LDCC68,1.0SQ针数:68
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.18
Is Samacsys:N最长访问时间:35 ns
其他特性:AUTOMATIC POWER-DOWNI/O 类型:COMMON
JESD-30 代码:S-PQCC-J68JESD-609代码:e0
长度:24.2062 mm内存密度:32768 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:16
湿度敏感等级:1功能数量:1
端口数量:2端子数量:68
字数:2048 words字数代码:2000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:2KX16
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC68,1.0SQ封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not Qualified座面最大高度:4.57 mm
最大待机电流:0.0015 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.25 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:24.2062 mm
Base Number Matches:1

IDT7143LA35J 数据手册

 浏览型号IDT7143LA35J的Datasheet PDF文件第2页浏览型号IDT7143LA35J的Datasheet PDF文件第3页浏览型号IDT7143LA35J的Datasheet PDF文件第4页浏览型号IDT7143LA35J的Datasheet PDF文件第5页浏览型号IDT7143LA35J的Datasheet PDF文件第6页浏览型号IDT7143LA35J的Datasheet PDF文件第7页 
IDT7133SA/LA  
IDT7143SA/LA  
HIGH SPEED  
2K X 16 DUAL-PORT  
SRAM  
Features  
High-speed access  
BUSY output flag on IDT7133; BUSY input on IDT7143  
Fully asynchronous operation from either port  
Military:25/35/45/55/70/90ns(max.)  
Industrial:25/35/55ns(max.)  
Commercial:20/25/35/45/55/70/90ns(max.)  
Battery backup operation–2V data retention  
TTL-compatible; single 5V (±10%) power supply  
Available in 68-pin ceramic PGA, Flatpack, PLCC and 100-  
pin TQFP  
Military product compliant to MIL-PRF-38535 QML  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Low-power operation  
IDT7133/43SA  
Active:1150mW(typ.)  
Standby: 5mW (typ.)  
IDT7133/43LA  
Active:1050mW(typ.)  
Standby: 1mW (typ.)  
Versatile control for write: separate write control for lower  
and upper byte of each port  
MASTER IDT7133 easily expands data bus width to 32 bits  
or more using SLAVE IDT7143  
On-chip port arbitration logic (IDT7133 only)  
Description  
The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static RAMs.  
The IDT7133is designedtobe usedas a stand-alone 16-bitDual-Port  
RAM or as a MASTER” Dual-Port RAM together with the IDT7143  
SLAVE” Dual-Port in 32-bit-or-more word width systems. Using the  
IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit-or-wider  
Functional Block Diagram  
R/WRUB  
CER  
R/WLUB  
CEL  
R/WLLB  
OEL  
R/WRLB  
OER  
I/O8R - I/O15R  
I/O0R - I/O7R  
I/O8L - I/O15L  
I/O0L - I/O7L  
I/O  
CONTROL  
I/O  
CONTROL  
(1)  
(1)  
BUSYR  
BUSYL  
A10R  
A10L  
MEMORY  
ARRAY  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
A0L  
A0R  
11  
11  
ARBITRATION  
LOGIC  
CER  
CEL  
(IDT7133 ONLY)  
2746 drw 01  
NOTE:  
1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor.  
IDT7143 (SLAVE): BUSY is input.  
JUNE 2000  
1
DSC 2746/11  
©2000IntegratedDeviceTechnology,Inc.  

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