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IDT7143LA45G PDF预览

IDT7143LA45G

更新时间: 2024-11-25 23:01:11
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
16页 141K
描述
HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS

IDT7143LA45G 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:PGA包装说明:CERAMIC, PGA-68
针数:68Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.68最长访问时间:45 ns
其他特性:AUTOMATIC POWER-DOWNI/O 类型:COMMON
JESD-30 代码:S-CPGA-P68JESD-609代码:e0
长度:29.464 mm内存密度:32768 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:16
功能数量:1端口数量:2
端子数量:68字数:2048 words
字数代码:2000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2KX16输出特性:3-STATE
可输出:YES封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:PGA封装等效代码:PGA68,11X11
封装形状:SQUARE封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
座面最大高度:3.683 mm最大待机电流:0.0015 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.25 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:PIN/PEG端子节距:2.54 mm
端子位置:PERPENDICULAR处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:29.464 mmBase Number Matches:1

IDT7143LA45G 数据手册

 浏览型号IDT7143LA45G的Datasheet PDF文件第2页浏览型号IDT7143LA45G的Datasheet PDF文件第3页浏览型号IDT7143LA45G的Datasheet PDF文件第4页浏览型号IDT7143LA45G的Datasheet PDF文件第5页浏览型号IDT7143LA45G的Datasheet PDF文件第6页浏览型号IDT7143LA45G的Datasheet PDF文件第7页 
IDT7133SA/LA  
IDT7143SA/LA  
HIGH SPEED  
2K X 16 DUAL-PORT  
SRAM  
Features  
High-speed access  
BUSY output flag on IDT7133; BUSY input on IDT7143  
Fully asynchronous operation from either port  
Military:25/35/45/55/70/90ns(max.)  
Industrial:25/35/55ns(max.)  
Commercial:20/25/35/45/55/70/90ns(max.)  
Battery backup operation–2V data retention  
TTL-compatible; single 5V (±10%) power supply  
Available in 68-pin ceramic PGA, Flatpack, PLCC and 100-  
pin TQFP  
Military product compliant to MIL-PRF-38535 QML  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Low-power operation  
IDT7133/43SA  
Active:1150mW(typ.)  
Standby: 5mW (typ.)  
IDT7133/43LA  
Active:1050mW(typ.)  
Standby: 1mW (typ.)  
Versatile control for write: separate write control for lower  
and upper byte of each port  
MASTER IDT7133 easily expands data bus width to 32 bits  
or more using SLAVE IDT7143  
On-chip port arbitration logic (IDT7133 only)  
Description  
The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static RAMs.  
The IDT7133is designedtobe usedas a stand-alone 16-bitDual-Port  
RAM or as a MASTER” Dual-Port RAM together with the IDT7143  
SLAVE” Dual-Port in 32-bit-or-more word width systems. Using the  
IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit-or-wider  
Functional Block Diagram  
R/WRUB  
CER  
R/WLUB  
CEL  
R/WLLB  
OEL  
R/WRLB  
OER  
I/O8R - I/O15R  
I/O0R - I/O7R  
I/O8L - I/O15L  
I/O0L - I/O7L  
I/O  
CONTROL  
I/O  
CONTROL  
(1)  
(1)  
BUSYR  
BUSYL  
A10R  
A10L  
MEMORY  
ARRAY  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
A0L  
A0R  
11  
11  
ARBITRATION  
LOGIC  
CER  
CEL  
(IDT7133 ONLY)  
2746 drw 01  
NOTE:  
1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor.  
IDT7143 (SLAVE): BUSY is input.  
JUNE 2000  
1
DSC 2746/11  
©2000IntegratedDeviceTechnology,Inc.  

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