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IDT71256L100L32B8 PDF预览

IDT71256L100L32B8

更新时间： 2024-11-16 20:55:31
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
16页 161K
描述
Standard SRAM, 32KX8, 100ns, CMOS, CQCC32, LCC-32

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IDT71256L100L32B8 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFJ包装说明：LCC-32
针数：32Reach Compliance Code：not_compliant
ECCN代码：3A001.A.2.CHTS代码：8542.32.00.41
风险等级：5.11最长访问时间：100 ns
I/O 类型：COMMONJESD-30 代码：R-CQCC-N32
JESD-609代码：e0长度：13.97 mm
内存密度：262144 bit内存集成电路类型：STANDARD SRAM
内存宽度：8功能数量：1
端口数量：1端子数量：32
字数：32768 words字数代码：32000
工作模式：ASYNCHRONOUS最高工作温度：125 °C
最低工作温度：-55 °C组织：32KX8
输出特性：3-STATE可输出：YES
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：QCCN
封装等效代码：LCC32,.45X.55封装形状：RECTANGULAR
封装形式：CHIP CARRIER并行/串行：PARALLEL
峰值回流温度（摄氏度）：225电源：5 V
认证状态：Not Qualified筛选级别：MIL-STD-883 Class B
座面最大高度：3.048 mm最大待机电流：0.0005 A
最小待机电流：2 V子类别：SRAMs
最大压摆率：0.125 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：NO LEAD端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：11.43 mmBase Number Matches：1

IDT71256L100L32B8 数据手册

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BiCMOS Static RAM  
IDT71216  
240K (16K x 15-Bit)  
Cache-Tag RAM  
for PowerPC™ and RISC Processors  
stored TAG bits and the current Tag input data. An active HIGH  
MATCH output is generated when these two groups of data are the  
same for a given address. This high-speed MATCH signal, with tADM  
as fast as 8ns, provides the fastest possible enabling of secondary  
cache accesses.  
Features  
◆
16K x 15 Configuration  
– 12 TAG Bits  
– 3 Separate I/O Status Bits (Valid, Dirty, Write Through)  
Match output uses Valid bit to qualify MATCH output  
High-Speed Address-to-Match comparison times  
◆
The three separate I/O status bits (VLD, DTY, and WT) can be  
configured for either dedicated or generic functionality, depending on  
the SFUNC input pin. With SFUNC LOW, the status bits are defined  
and used internally by the device, allowing easier determination of  
the validity and use of the given Tag data. SFUNC HIGH releases the  
defined internal status bit usage and control, allowing the user to  
configure the status bit information to fit his system needs. A synchro-  
nous RESET pin, when held LOW at a rising clock edge, will reset all  
status bits in the array for easy invalidation of all Tag addresses.  
The IDT71216 also provides the option for Transfer Acknowledge  
(TA) generation within the cache tag itself, based upon MATCH, VLD  
bit, WT bit, and external inputs provided by the user. This can  
significantly simplify cache controller logic and minimize cache  
decision time. Match and Read operations are both asynchronous  
in order to provide the fastest access times possible, while Write  
operations are synchronous for ease of system timing.  
The IDT71216 uses a 5V power supply on Vcc, with separate  
VCCQ pins provided for the outputs to offer compliance with both 5V  
TTL and 3.3V LVTTL Logic levels. The PWRDN pin offers a low-  
power standby mode to reduce power consumption by 90%, provid-  
ing significant system power savings.  
The IDT71216 is fabricated using IDT’s high-performance, high-  
reliability BiCMOS technology and is offered in a space-saving 80-  
pin plastic Thin Quad Flat Pack (TQFP) package.  
◆
– 8/9/10/12ns over commercial temperature range  
TA circuitry included inside the Cache-Tag for highest  
speed operation  
◆
◆
Asynchronous Read/Match operation with Synchronous  
Write and Reset operation  
◆
Separate WE for the TAG bits and the Status bits  
◆
Separate OE for the TAG bits, the Status bits, and TA  
◆
Synchronous RESET pin for invalidation of all Tag  
entries  
◆
Dual Chip selects for easy depth expansion with no  
performance degredation  
I/O pins both 5V TTL and 3.3V LVTTL compatible with  
◆
VCCQ pins  
◆
PWRDN pin to place device in low-power mode  
Packaged in a 80-pin plastic Thin Quad Flat Pack (TQFP).  
◆
Description  
The IDT71216 is a 245,760-bit Cache Tag Static RAM, orga-  
nized 16K x 15 and designed to support PowerPC and other RISC  
processors at bus speeds up to 66MHz. There are twelve common  
I/O TAG bits, with the remaining three bits used as status bits. A 12-  
bit comparator is on-chip to allow fast comparison of the twelve  
Pin Descriptions  
0
13  
A – A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
CLK  
TAH  
System Clock  
Input  
Input  
Input  
Input  
Output  
I/O  
Chip Selects  
CS1, CS2  
WET  
TA Force High  
Write Enable – Tag Bits  
Write Enable – Status Bits  
Output Enable – Tag Bits  
Output Enable – Status Bits  
Status Bit Reset  
TAOE  
TAIN  
TA  
TA Output Enable  
Additional TA Input  
Transfer Acknowledge  
Tag Data Input/Outputs  
WES  
OET  
0
11  
TAG – TAG  
OES  
OUT 1OUT  
VLD /S  
1
Valid Bit/S Bit Output  
Output  
Output  
RESET  
PWRDN  
SFUNC  
TT1  
OUT 2OUT  
DTY /S  
2
Powerdown Mode Control Pin  
Status Bit Function Control Pin  
Dirty Bit/S Bit Output  
OUT 3OUT  
WT /S  
3
Write Through Bit/S Bit Output Output  
Read/Write Input from Processor Input  
MATCH  
Match  
Output  
Pwr  
IN 1IN  
1
CC  
V
VLD /S  
Valid Bit/S Bit Input  
Input  
Input  
Input  
+5V Power  
Output Buffer Power  
Ground  
IN 2IN  
2
CCQ  
V
DTY /S  
Dirty Bit/S Bit Input  
QPwr  
Gnd  
IN 3IN  
3
SS  
V
WT /S  
Write Through Bit/S Bit Input  
3067 tbl 01  
PowerPC is a trademark of International Business Machines, Inc.  
OCTOBER 1999  
1
©1999 Integrated Device Technology, Inc.  
DSC-3067/04  
1234567...16

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