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IDT71128S12Y8 PDF预览

IDT71128S12Y8

更新时间: 2024-11-16 14:51:23
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
8页 79K
描述
Standard SRAM, 256KX4, 12ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32

IDT71128S12Y8 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOJ包装说明:0.400 INCH, PLASTIC, SOJ-32
针数:32Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.92Is Samacsys:N
最长访问时间:12 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-J32JESD-609代码:e0
长度:20.955 mm内存密度:1048576 bit
内存集成电路类型:STANDARD SRAM内存宽度:4
湿度敏感等级:3功能数量:1
端口数量:1端子数量:32
字数:262144 words字数代码:256000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256KX4
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ32,.44封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not Qualified座面最大高度:3.683 mm
最大待机电流:0.01 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.155 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:10.16 mm
Base Number Matches:1

IDT71128S12Y8 数据手册

 浏览型号IDT71128S12Y8的Datasheet PDF文件第2页浏览型号IDT71128S12Y8的Datasheet PDF文件第3页浏览型号IDT71128S12Y8的Datasheet PDF文件第4页浏览型号IDT71128S12Y8的Datasheet PDF文件第5页浏览型号IDT71128S12Y8的Datasheet PDF文件第6页浏览型号IDT71128S12Y8的Datasheet PDF文件第7页 
CMOS Static RAM  
1 Meg (256K x 4-Bit)  
Revolutionary Pinout  
IDT71128  
Description  
Features  
The IDT71128 is a 1,048,576-bit high-speed static RAM  
organized as 256K x 4. It is fabricated using IDTs high-perfor-  
mance, high-reliability CMOS technology. This state-of-the-art  
technology, combined with innovative circuit design techniques,  
provides a cost-effective solution for high-speed memory needs.  
The JEDEC centerpower/GND pinout reduces noise generation  
and improves system performance.  
256K x 4 advanced high-speed CMOS static RAM  
JEDEC revolutionary pinout (center power/GND) for  
reduced noise.  
Equal access and cycle times  
— Commercial and Industrial: 12/15/20ns  
One Chip Select plus one Output Enable pin  
Bidirectional inputs and outputs directly  
The IDT71128 has an output enable pin which operates as fast  
as 6ns, with address access times as fast as 12ns available. All  
bidirectional inputs and outputs of the IDT71128 are TTL-compat-  
ible and operation is from a single 5V supply. Fully static asyn-  
chronous circuitry is used; no clocks or refreshes are required for  
operation.  
TTL-compatible  
Low power consumption via chip deselect  
Available in a 32-pin 400 mil Plastic SOJ.  
The IDT71128 is packaged in a 32-pin 400 mil Plastic SOJ.  
Functional Block Diagram  
A0  
1,048,576-BIT  
MEMORY  
ARRAY  
ADDRESS  
DECODER  
.
A17  
4
4
I/O0 - I/O3  
I/O CONTROL  
CS  
WE  
OE  
CONTROL  
LOGIC  
3483 drw 01  
FEBRUARY 2001  
DSC-3483/09  
1
©2000IntegratedDeviceTechnology,Inc.  

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