Datasheet > IDT71215S9PF9

IDT71215S9PF9

更新时间： 2024-11-17 03:28:27

品牌	Logo	应用领域
艾迪悌 - IDT		信息通信管理静态存储器
页数	文件大小	规格书
16页	164K
描述
Cache Tag SRAM, 16KX15, 9ns, BICMOS, PQFP80, PLASTIC, TQFP-80

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IDT71215S9PF9 数据手册

BiCMOS Static RAM

240K (16K x 15-Bit)

Cache-Tag RAM

IDT71215

for the Pentium™ Processor

stored TAG bits and the current Tag input data. An active HIGH

MATCH output is generated when these two groups of data are the

same for a given address. This high-speed MATCH signal, with tADM

as fast as 8ns, provides the fastest possible enabling of secondary

cache accesses.

Features

◆

16K x 15 Configuration

– 12 TAG Bits

– 3 Separate I/O Status Bits (Valid, Dirty, Write Through)

Match output uses Valid bit to qualify MATCH output

High-Speed Address-to-Match comparison times

◆

The three separate I/O status bits (VLD, DTY, and WT) can be

configured for either dedicated or generic functionality, depending on

the SFUNC input pin. With SFUNC LOW, the status bits are defined

and used internally by the device, allowing easier determination of the

validity and use of the given Tag data. SFUNC HIGH releases the

defined internal status bit usage and control, allowing the user to

configure the status bit information to fit his system needs. A synchro-

nous RESET pin, when held LOW at a rising clock edge, will reset all

status bits in the array for easy invalidation of all Tag addresses.

The IDT71215 also provides the option for Burst Ready (BRDY)

generation within the cache tag itself, based upon MATCH, VLD bit,

WT bit, and external inputs provided by the user. This can significantly

simplify cache controller logic and minimize cache decision time.

Match and Read operations are both asynchronous in order to

provide the fastest access times possible, while Write operations are

synchronous for ease of system timing.

The IDT71215 uses a 5V power supply on VCC with separate VCCQ

pins provided for the outputs to offer compliance with both 5V TTL and

3.3V LVTTL Logic levels. The PWRDN pin offers a low-power standby

mode to reduce power consumption by 90%, providing significant

system power savings.

The IDT71215 is fabricated using IDT’s high-performance, high-

reliability BiCMOS technology and is offered in a space-saving 80-pin

Thin Plastic Quad Flat Pack (TQFP) package.

◆

– 8/9/10/12ns over commercial temperature range

BRDY circuitry included inside the Cache-Tag for

highest speed operation

◆

Asynchronous Read/Match operation with Synchronous

Write and Reset operation

◆

Separate WE for the TAG bits and the Status bits

◆

Separate OE for the TAG bits, the Status bits, and BRDY

◆

Synchronous RESET pin for invalidation of all Tag

entries

◆

Dual Chip selects for easy depth expansion with no

performance degredation

I/O pins both 5V TTL and 3.3V LVTTL compatible with

◆

VCCQ pins

◆

PWRDN pin to place device in low-power mode

Packaged in a 80-pin Thin Plastic Quad Flat Pack (TQFP).

◆

Description

The IDT71215 is a 245,760-bit Cache Tag Static RAM, orga-

nized 16K x 15 and designed to support the Pentium and other Intel

processors at bus speeds up to 66MHz. There are twelve common

I/O TAG bits, with the remaining three bits used as status bits. A 12-

bit comparator is on-chip to allow fast comparison of the twelve

Pin Descriptions

A – A

Address Inputs

Input

CLK

System Clock

Input

Output

I/O

Chip Selects

BRDYH

CS1, CS2

WET

BRDY Force High

BRDY Output Enable

Additional BRDY Input

Burst Ready

Write Enable – Tag Bits

Write Enable – Status Bits

Output Enable – Tag Bits

Output Enable – Status Bits

Status Bit Reset

BRDYOE

BRDYIN

BRDY

WES

OET

TAG – TAG

Tag Data Input/Outputs

OES

OUT 1OUT

VLD /S

Valid Bit/S Bit Output

Output

RESET

PWRDN

SFUNC

W/R

OUT 2OUT

DTY /S

Powerdown Mode Control Pin

Status Bit Function Control Pin

Dirty Bit/S Bit Output

OUT 3OUT

WT /S

Write Through Bit/S Bit Output Output

Write/Read Input from Processor Input

MATCH

Match

Output

Pwr

IN 1IN

VLD /S

Valid Bit/S Bit Input

Input

+5V Power

Output Buffer Power

Ground

IN 2IN

CCQ

DTY /S

Dirty Bit/S Bit Input

QPwr

Gnd

IN 3IN

WT /S

Write Through Bit/S Bit Input

3075 tbl 01

Pentium is a trademark of Intel Corporation.

OCTOBER 1999

DSC-3075/04

12 3 4 5 6 7...16

中文翻译

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与IDT71215S9PF9相关器件

型号	品牌	获取价格	描述	数据表
IDT71216	IDT	获取价格	BiCMOS StaticRAM 240K (16K x 15-BIT) CACHE-TAG RAM For PowerPCO and RISC Processors
IDT71216S10PF	IDT	获取价格	BiCMOS StaticRAM 240K (16K x 15-BIT) CACHE-TAG RAM For PowerPCO and RISC Processors
IDT71216S10PF8	IDT	获取价格	Cache Tag SRAM, 16KX15, 12ns, BICMOS, PQFP80, PLASTIC, TQFP-80
IDT71216S10PF9	IDT	获取价格	Cache Tag SRAM, 16KX15, 12ns, BICMOS, PQFP80, PLASTIC, TQFP-80
IDT71216S12PF	IDT	获取价格	BiCMOS StaticRAM 240K (16K x 15-BIT) CACHE-TAG RAM For PowerPCO and RISC Processors
IDT71216S12PF8	IDT	获取价格	Cache Tag SRAM, 16KX15, 12ns, BICMOS, PQFP80, PLASTIC, TQFP-80
IDT71216S8PF	IDT	获取价格	BiCMOS StaticRAM 240K (16K x 15-BIT) CACHE-TAG RAM For PowerPCO and RISC Processors
IDT71216S8PF8	IDT	获取价格	Cache Tag SRAM, 16KX15, 10ns, BICMOS, PQFP80, PLASTIC, TQFP-80
IDT71216S8PF9	IDT	获取价格	Cache Tag SRAM, 16KX15, 10ns, BICMOS, PQFP80, PLASTIC, TQFP-80
IDT71216S9PF	IDT	获取价格	BiCMOS StaticRAM 240K (16K x 15-BIT) CACHE-TAG RAM For PowerPCO and RISC Processors

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