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IDT71216S12PF PDF预览

IDT71216S12PF

更新时间： 2024-09-28 22:35:19
品牌 Logo 应用领域
艾迪悌 - IDT 存储内存集成电路静态存储器输出元件信息通信管理PC
页数 文件大小 规格书
14页 158K
描述
BiCMOS StaticRAM 240K (16K x 15-BIT) CACHE-TAG RAM For PowerPCO and RISC Processors

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中文翻译

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IDT71216S12PF 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：PLASTIC, TQFP-80
针数：80Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.32.00.41
风险等级：5.83Is Samacsys：N
最长访问时间：14 ns其他特性：MATCH OUTPUT; 12-BIT TAG WIDTH; SYNCHRONOUS WRITE OPERATION
JESD-30 代码：S-PQFP-G80JESD-609代码：e0
长度：14 mm内存密度：245760 bit
内存集成电路类型：CACHE TAG SRAM内存宽度：15
湿度敏感等级：3功能数量：1
端口数量：1端子数量：80
字数：16384 words字数代码：16000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：16KX15
输出特性：3-STATE可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP80,.64SQ封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
电源：3.3/5,5 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.025 A
子类别：SRAMs最大压摆率：0.28 mA
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BICMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
宽度：14 mmBase Number Matches：1

IDT71216S12PF 数据手册

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BiCMOS StaticRAM  
IDT71216  
240K (16K x 15-BIT)  
CACHE-TAG RAM  
For PowerPC and RISC Processors  
Integrated Device Technology, Inc.  
This high-speed MATCH signal, with tADM as fast as 8ns,  
provides the fastest possible enabling of secondary cache  
accesses.  
FEATURES:  
• 16K x 15 Configuration  
– 12 TAG Bits  
The three separate I/O status bits (VLD, DTY, and WT) can  
be configured for either dedicated or generic functionality,  
depending on the SFUNC input pin. With SFUNC LOW, the  
status bits are defined and used internally by the device,  
allowing easier determination of the validity and use of the  
given Tag data. SFUNC HIGH releases the defined internal  
status bit usage and control, allowing the user to configure the  
status bit information to fit his system needs. A synchronous  
RESET pin, when held LOW at a rising clock edge, will reset  
all status bits in the array for easy invalidation of all Tag  
addresses.  
The IDT71216 also provides the option for Transfer Ac-  
knowledge (TA) generation within the cache tag itself, based  
upon MATCH, VLD bit, WT bit, and external inputs provided  
by the user. This can significantly simplify cache controller  
logic and minimize cache decision time. Match and Read  
operations are both asynchronous in order to provide the  
fastest access times possible, while Write operations are  
synchronous for ease of system timing.  
– 3 Separate I/O Status Bits (Valid, Dirty, Write Through)  
• Match output uses Valid bit to qualify MATCH output  
• High-Speed Address-to-Match comparison times  
– 8/9/10/12ns over commercial temperature range  
• TA circuitry included inside the Cache-Tag for highest  
speed operation  
• Asynchronous Read/Match operation with Synchronous  
Write and Reset operation  
• Separate WE for the TAG bits and the Status bits  
• Separate OE for the TAG bits, the Status bits, and TA  
• Synchronous RESET pin for invalidation of all Tag entries  
• Dual Chip selects for easy depth expansion with no  
performance degredation  
• I/O pins both 5V TTL and 3.3V LVTTL compatible with  
VCCQ pins  
• PWRDN pin to place device in low-power mode  
• Packaged in a 80-pin Thin Plastic Quad Flat Pack  
(TQFP)  
The IDT71216 uses a 5V power supply on Vcc, with  
separate VCCQ pins provided for the outputs to offer compli-  
ance with both 5.0V TTL and 3.3V LVTTL Logic levels. The  
PWRDN pin offers a low-power standby mode to reduce  
power consumption by 90%, providing significant system  
power savings.  
The IDT71216 is fabricated using IDT's high-performance,  
high-reliability BiCMOS technology and is offered in a space-  
saving 80-pin Thin Plastic Quad Flat Pack (TQFP) package.  
DESCRIPTION:  
The IDT71216 is a 245,760-bit Cache Tag StaticRAM,  
organized 16K x 15 and designed to support PowerPC and  
other RISC processors at bus speeds up to 66MHz. There are  
twelve common I/O TAG bits, with the remaining three bits  
usedasstatusbits. A12-bitcomparatorison-chiptoallowfast  
comparison of the twelve stored TAG bits and the current Tag  
input data. An active HIGH MATCH output is generated when  
these two groups of data are the same for a given address.  
PIN DESCRIPTIONS  
CLK  
TAH  
TAOE  
TAIN  
TA  
System Clock  
Input  
Input  
Input  
Input  
Output  
I/O  
A0 – A13  
CS1, CS2  
WET  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
TA Force High  
Chip Selects  
TA Output Enable  
Additional TA Input  
Transfer Acknowledge  
Write Enable - Tag Bits  
Write Enable - Status Bits  
Output Enable - Tag Bits  
Output Enable - Status Bits  
Status Bit Reset  
WES  
OET  
TAG0 – TAG11 Tag Data Input/Outputs  
VLDOUT / S1OUT Valid Bit / S1 Bit Output  
DTYOUT / S2OUT Dirty Bit / S2 Bit Output  
OES  
Output  
Output  
Output  
Output  
Pwr  
RESET  
PWRDN  
SFUNC  
TT1  
Powerdown Mode Control Pin  
Status Bit Function Control Pin  
Read/Write Input from Processor  
WTOUT / S3OUT  
MATCH  
VCC  
Write Through Bit / S3 Bit Output  
Match  
+5V Power  
Output Buffer Power  
Ground  
VLDIN / S1IN Valid Bit / S1 Bit Input  
DTYIN / S2IN Dirty Bit / S2 Bit Input  
VCCQ  
VSS  
QPwr  
Gnd  
WTIN / S3IN  
Write Through Bit / S3 Bit Input  
3067 tbl 01  
The IDT logo is a registered trademark and CacheRAM is a trademark of Integrated Device Technology, Inc.  
PowerPC is a trademark of International Business Machines, Inc.  
COMMERCIAL TEMPERATURE RANGE  
AUGUST 1996  
1996 Integrated Device Technology, Inc.  
DSC-3067/3  
14.3  
1
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中文翻译

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IDT71216S12PF 替代型号

型号 品牌 替代类型 描述 数据表
IDT71216S10PF IDT

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