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IDT70V7519S133BCGI8 PDF预览

IDT70V7519S133BCGI8

更新时间: 2024-11-25 14:33:59
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
22页 490K
描述
Dual-Port SRAM, 256KX36, 15ns, PBGA256, BGA-256

IDT70V7519S133BCGI8 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:BGA
包装说明:LBGA,针数:256
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.15
Is Samacsys:N最长访问时间:15 ns
其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTUREJESD-30 代码:S-PBGA-B256
JESD-609代码:e1长度:17 mm
内存密度:9437184 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:36湿度敏感等级:3
功能数量:1端子数量:256
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:256KX36
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.5 mm
最大供电电压 (Vsup):3.45 V最小供电电压 (Vsup):3.15 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:17 mm
Base Number Matches:1

IDT70V7519S133BCGI8 数据手册

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HIGH-SPEED 3.3V 256K x 36  
SYNCHRONOUS  
BANK-SWITCHABLE  
IDT70V7519S  
DUAL-PORT STATIC RAM  
WITH 3.3V OR 2.5V INTERFACE  
Features:  
– 1.5ns setup to clock and 0.5ns hold on all control, data, and  
address inputs @ 200MHz  
Data input, address, byte enable and control registers  
– Self-timedwriteallowsfastcycletime  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
LVTTL- compatible, 3.3V (±150mV) power supply  
for core  
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V  
(±100mV) power supply for I/Os and control signals on  
each port  
Industrial temperature range (-40°C to +85°C) is  
available at 166MHz and 133MHz  
Available in a 208-pin Plastic Quad Flatpack (PQFP),  
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball  
GridArray(BGA)  
256K x 36 Synchronous Bank-Switchable Dual-ported  
SRAM Architecture  
64 independent 4K x 36 banks  
– 9 megabits of memory on chip  
Bank access controlled via bank address pins  
High-speed data access  
– Commercial:3.4ns(200MHz)/3.6ns(166MHz)/4.2ns  
(133MHz) (max.)  
Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)  
Selectable Pipelined or Flow-Through output mode  
Counter enable and repeat features  
Dual chip enables allow for depth expansion without  
additional logic  
Full synchronous operation on both ports  
– 5ns cycle time, 200MHzoperation(14Gbps bandwidth)  
– Fast 3.4ns clock to data out  
Supports JTAG features compliant with IEEE 1149.1  
FunctionalBlockDiagram  
PL/FTL  
OPTL  
PL/FTR  
OPTR  
CLKL  
CLKR  
ADSL  
ADSR  
CNTENL  
REPEATL  
R/WL  
CNTENR  
REPEATR  
R/WR  
CE0R  
CE1R  
BE3R  
BE2R  
BE1R  
BE0R  
OER  
MUX  
CE0L  
CE1L  
BE3L  
BE2L  
BE1L  
BE0L  
OEL  
CONTROL  
LOGIC  
CONTROL  
LOGIC  
4Kx36  
MEMORY  
ARRAY  
(BANK 0)  
MUX  
MUX  
I/O  
CONTROL  
I/O  
I/O0L-35L  
I/O0R-35R  
CONTROL  
4Kx36  
MEMORY  
ARRAY  
A11R  
(BANK 1)  
A11L  
A0L  
ADDRESS  
ADDRESS  
DECODE  
DECODE  
A0R  
MUX  
BA5R  
BA4R  
BA5L  
BA4L  
BA3R  
BA2R  
BA1R  
BA0R  
BANK  
DECODE  
BA  
BA  
3L  
BANK  
DECODE  
2L  
BA1L  
BA0L  
MUX  
4Kx36  
MEMORY  
ARRAY  
(BANK 63)  
NOTE:  
MUX  
1. The Bank-Switchable dual-port uses a true SRAM  
core instead of the traditional dual-port SRAM core.  
As a result, it has unique operating characteristics.  
Please refer to the functional description on page 19  
for details.  
,
5618 drw 01  
TMS  
TCK  
TRST  
TDI  
TDO  
JTAG  
DECEMBER 2002  
1
DSC 5618/5  
©2002IntegratedDeviceTechnology,Inc.  

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