Datasheet > IDT70T9169L9PF1

IDT70T9169L9PF1

更新时间： 2024-11-28 03:15:23

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
16页	190K
描述
HIGH-SPEED 2.5V 16/8K X 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

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中文翻译

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数据手册

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IDT70T9169L9PF1 数据手册

PRELIMINARY

IDT70T9169/59L

HIGH-SPEED 2.5V

16/8K X 9 SYNCHRONOUS

PIPELINED

DUAL-PORT STATIC RAM

ꢀeatures

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

– Commercial:7.5/9/12ns(max.)

– Industrial:9ns (max.)

Full synchronous operation on both ports

– 4.0ns setup to clock and 0.5ns hold on all control, data, and

addressinputs

– Data input, address, and control registers

– Fast 7.5ns clock to data out in the Pipelined output mode

– Self-timedwriteallowsfastcycletime

◆

Low-power operation

– IDT70T9169/59L

– 12ns cycle time, 83MHz operation in Pipelined output mode

LVTTL- compatible, single 2.5V (±100mV) power supply

Industrial temperature range (–40°C to +85°C) is

available for 66MHz

Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-

pin fine pitch Ball Grid Array (fpBGA) packages.

◆

Active:225mW(typ.)

Standby: 1.5mW (typ.)

◆

Flow-Through or Pipelined output mode on either Port via

the FT/PIPE pins

Counter enable and reset features

Dual chip enables allow for depth expansion without

additional logic

◆

ꢀunctional Block Diagram

R/W

CE0R

CE1R

CE0L

CE1L

0/1

FT/PIPE

0/1

FT/PIPE

I/O0R - I/O8R

I/O0L - I/O8L

I/O

Control

I/O

Control

(1)

13L

13R

Counter/

Address

Reg.

Counter/

Address

Reg.

MEMORY

ARRAY

CLK

ADS

CNTEN

CLK

ADS

CNTEN

CNTRST

5654 drw 01

NOTE:

1. A¹³is a NC for IDT70T9159.

JULY 2002

DSC-5654/1

12 3 4 5 6 7...16

中文翻译

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