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IDT70T9169L7PF8 PDF预览

IDT70T9169L7PF8

更新时间: 2024-10-29 14:38:03
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
16页 295K
描述
Multi-Port SRAM, 16KX9, 18ns, CMOS, PQFP100

IDT70T9169L7PF8 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:ObsoleteReach Compliance Code:not_compliant
风险等级:5.92Is Samacsys:N
最长访问时间:18 ns最大时钟频率 (fCLK):83 MHz
I/O 类型:COMMONJESD-30 代码:S-PQFP-G100
JESD-609代码:e0内存密度:147456 bit
内存集成电路类型:MULTI-PORT SRAM内存宽度:9
湿度敏感等级:3端口数量:2
端子数量:100字数:16384 words
字数代码:16000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16KX9输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:2.5 V
认证状态:Not Qualified最大待机电流:0.003 A
最小待机电流:2.4 V子类别:SRAMs
最大压摆率:0.2 mA标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
Base Number Matches:1

IDT70T9169L7PF8 数据手册

 浏览型号IDT70T9169L7PF8的Datasheet PDF文件第2页浏览型号IDT70T9169L7PF8的Datasheet PDF文件第3页浏览型号IDT70T9169L7PF8的Datasheet PDF文件第4页浏览型号IDT70T9169L7PF8的Datasheet PDF文件第5页浏览型号IDT70T9169L7PF8的Datasheet PDF文件第6页浏览型号IDT70T9169L7PF8的Datasheet PDF文件第7页 
HIGH-SPEED 2.5V  
IDT70T9169/59L  
16/8K X 9 SYNCHRONOUS  
PIPELINED  
DUAL-PORT STATIC RAM  
Features  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial:7.5/9/12ns(max.)  
– Industrial: 9ns (max.)  
Full synchronous operation on both ports  
– 4.0ns setup to clock and 0.5ns hold on all control, data, and  
addressinputs  
– Data input, address, and control registers  
– Fast 7.5ns clock to data out in the Pipelined output mode  
– Self-timedwriteallowsfastcycletime  
Low-power operation  
– IDT70T9169/59L  
– 12ns cycle time, 83MHz operation in Pipelined output mode  
LVTTL- compatible, single 2.5V (±100mV) power supply  
Industrial temperature range (–40°C to +85°C) is  
available for 66MHz  
Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-  
pin fine pitch Ball Grid Array (fpBGA) packages.  
Active:225mW(typ.)  
Standby: 1.5mW (typ.)  
Flow-Through or Pipelined output mode on either Port via  
the FT/PIPE pins  
Counter enable and reset features  
Dual chip enables allow for depth expansion without  
additional logic  
Functional Block Diagram  
R/WR  
R/W  
L
OEL  
OER  
CE0R  
CE1R  
CE0L  
CE1L  
1
0
0/1  
1
0
0/1  
0
0
1
1
0/1  
0/1  
FT/PIPE  
L
FT/PIPE  
R
I/O0R - I/O8R  
I/O0L - I/O8L  
I/O  
Control  
I/O  
Control  
(1)  
(1)  
13R  
A13L  
A
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
MEMORY  
ARRAY  
A
C0LRK  
R
R
A
0L  
CLK  
L
L
ADS  
CNTEN  
CNTRST  
ADS  
CNTEN  
CNTRST  
R
L
R
L
5654 drw 01  
NOTE:  
1. A13 is a NC for IDT70T9159.  
AUGUST 2004  
1
DSC-5654/2  
©2004 IntegratedDeviceTechnology,Inc.  

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