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IDT70T9169L7BF PDF预览

IDT70T9169L7BF

更新时间: 2024-11-25 05:12:11
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
16页 190K
描述
HIGH-SPEED 2.5V 16/8K X 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

IDT70T9169L7BF 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:FPBGA-100针数:100
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.92
最长访问时间:18 ns其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE
最大时钟频率 (fCLK):83 MHzI/O 类型:COMMON
JESD-30 代码:S-PBGA-B100JESD-609代码:e0
长度:10 mm内存密度:147456 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:9
湿度敏感等级:3功能数量:1
端口数量:2端子数量:100
字数:16384 words字数代码:16000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:16KX9
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装等效代码:BGA100,10X10,32
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:2.5 V认证状态:Not Qualified
座面最大高度:1.5 mm最大待机电流:0.003 A
最小待机电流:2.4 V子类别:SRAMs
最大压摆率:0.2 mA最大供电电压 (Vsup):2.6 V
最小供电电压 (Vsup):2.4 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn63Pb37)
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:10 mmBase Number Matches:1

IDT70T9169L7BF 数据手册

 浏览型号IDT70T9169L7BF的Datasheet PDF文件第2页浏览型号IDT70T9169L7BF的Datasheet PDF文件第3页浏览型号IDT70T9169L7BF的Datasheet PDF文件第4页浏览型号IDT70T9169L7BF的Datasheet PDF文件第5页浏览型号IDT70T9169L7BF的Datasheet PDF文件第6页浏览型号IDT70T9169L7BF的Datasheet PDF文件第7页 
PRELIMINARY  
IDT70T9169/59L  
HIGH-SPEED 2.5V  
16/8K X 9 SYNCHRONOUS  
PIPELINED  
DUAL-PORT STATIC RAM  
ꢀeatures  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial:7.5/9/12ns(max.)  
Industrial:9ns (max.)  
Full synchronous operation on both ports  
4.0ns setup to clock and 0.5ns hold on all control, data, and  
addressinputs  
Data input, address, and control registers  
Fast 7.5ns clock to data out in the Pipelined output mode  
Self-timedwriteallowsfastcycletime  
Low-power operation  
IDT70T9169/59L  
12ns cycle time, 83MHz operation in Pipelined output mode  
LVTTL- compatible, single 2.5V (±100mV) power supply  
Industrial temperature range (–40°C to +85°C) is  
available for 66MHz  
Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-  
pin fine pitch Ball Grid Array (fpBGA) packages.  
Active:225mW(typ.)  
Standby: 1.5mW (typ.)  
Flow-Through or Pipelined output mode on either Port via  
the FT/PIPE pins  
Counter enable and reset features  
Dual chip enables allow for depth expansion without  
additional logic  
ꢀunctional Block Diagram  
R/W  
R
W
L
R/  
OE  
L
OE  
R
CE0R  
CE1R  
CE0L  
CE1L  
1
0
0/1  
1
0
0/1  
0
0
1
1
FT/PIPE  
0/1  
0/1  
L
FT/PIPE  
R
I/O0R - I/O8R  
I/O0L - I/O8L  
I/O  
Control  
I/O  
Control  
(1)  
(1)  
A
13L  
A
13R  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
MEMORY  
ARRAY  
A
0R  
A
0L  
CLK  
ADS  
CNTEN  
R
R
CLK  
L
L
L
L
ADS  
CNTEN  
CNTRST  
R
CNTRST  
R
5654 drw 01  
NOTE:  
1. A13 is a NC for IDT70T9159.  
JULY 2002  
1
DSC-5654/1  
©2002IntegratedDeviceTechnology,Inc.  

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