Datasheet > IDT70T659S15DR8

IDT70T659S15DR8

更新时间： 2024-10-30 05:38:31

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
27页	231K
描述
Multi-Port SRAM, 128KX36, 15ns, CMOS, PQFP208

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中文翻译

获取价格

数据手册

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IDT70T659S15DR8 数据手册

IDT70T651/9S

HIGH-SPEED 2.5V

256/128K x 36

ASYNCHRONOUS DUAL-PORT

STATIC RAM

WITH 3.3V 0R 2.5V INTERFACE

◆

On-chip port arbitration logic

Features

◆

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed access

◆

– Commercial:8/10/12/15ns(max.)

– Industrial:10/12ns (max.)

◆

Sleep Mode Inputs on both ports

RapidWrite Mode simplifies high-speed consecutive write

Supports JTAG features compliant to IEEE 1149.1

Single 2.5V (±100mV) power supply for core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Available in a 256-ball Ball Grid Array, 208-pin Plastic Quad

Flatpack and 208-ball fine pitch Ball Grid Array.

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

cycles

◆

Dual chip enables allow for depth expansion without

external logic

◆

IDT70T651/9 easily expands data bus width to 72 bits or

more using the Master/Slave select when cascading more

than one device

◆

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Busy and Interrupt Flags

◆

Green parts available, see ordering information

Functional Block Diagram

BE3L

BE3R

BE2R

BE2L

BE1L

BE0L

BE1R

BE0R

R/WL

R/WR

B B B B

E E E E

B B B

E E E

2 1 0

CE0L

CE1L

CE0R

CE1R

R R R R

OEL

OER

Dout0-8_L

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout0-8_R

Dout9-17_R

Dout18-26_R

Dout27-35_R

256/128K x 36

MEMORY

ARRAY

I/O0L- I/O35L

Di n_L

Di n_R

I/O0R -I/O35R

(1)

17R

(1)

17L

Address

Decoder

Address

Decoder

ADDR_L

ADDR_R

A0L

CE0L

CE1L

ARBITRATION

CE0R

CE1R

TDI

TC K

TMS

TRST

JTAG

INTERRUPT

SEMAPHORE

LOGIC

TD O

R/WL

R/W

(2,3)

(3)

(2,3)

BUSY

SEM

M/S

SEM

(3)

INT

(4)

ZZR

ZZL

CONTROL

LOGIC

NOTES:

1. Address A^17xis a NC for IDT70T659.

2. BUSY is an input as a Slave (M/S=V^IL) and an output when it is a Master (M/S=VIH).

3. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

4869 drw 01

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep

mode pins themselves (ZZx) are not affected during sleep mode.

JANUARY 2006

DSC-5632/5

12 3 4 5 6 7...27

中文翻译

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与IDT70T659S15DR8相关器件

型号	品牌	获取价格	描述	数据表
IDT70T659S15DRG	IDT	获取价格	Dual-Port SRAM, 128KX36, 15ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM PITCH, GREEN, PLASTIC, Q
IDT70T659S15DRI	IDT	获取价格	HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFAC
IDT70T659S8BC	IDT	获取价格	HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFAC
IDT70T659S8BC8	IDT	获取价格	Dual-Port SRAM, 128KX36, 8ns, CMOS, PBGA256, BGA-256
IDT70T659S8BCG8	IDT	获取价格	Multi-Port SRAM, 128KX36, 8ns, CMOS, PBGA256
IDT70T659S8BCI	IDT	获取价格	HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFAC
IDT70T659S8BF	IDT	获取价格	HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFAC
IDT70T659S8BF8	IDT	获取价格	Dual-Port SRAM, 128KX36, 8ns, CMOS, PBGA208, FBGA-208
IDT70T659S8BFG8	IDT	获取价格	Dual-Port SRAM, 128KX36, 8ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM PITCH, GREEN, FBGA-208
IDT70T659S8BFI	IDT	获取价格	HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFAC

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