Datasheet > IDT709169L9BF

IDT709169L9BF

更新时间： 2024-09-16 05:28:51

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
16页	179K
描述
Dual-Port SRAM, 16KX9, 20ns, CMOS, PBGA100, 10 X 10 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FPBGA-100

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中文翻译

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数据手册

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IDT709169L9BF 数据手册

HIGH-SPEED 16/8K x 9

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

IDT709169/59L

Features

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

– Commercial:6.5/7.5/9ns(max.)

Industrial:7.5ns (max.)

Full synchronous operation on both ports

– 3.5ns setup to clock and 0ns hold on all control, data, and

address inputs

– Data input, address, and control registers

– Fast 6.5ns clock to data out in the Pipelined output mode

– Self-timed write allows fast cycle time

◆

Low-power operation

– IDT709169/59L

– 10ns cycle time,100MHzoperationinPipelinedoutputmode

TTL- compatible, single 5V (±10%) power supply

Industrial temperature range (–40°C to +85°C) is

available for 83MHz

Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-

pin fine pitch Ball Grid Array (fpBGA) packages.

◆

Active:925mW(typ.)

Standby: 2.5mW (typ.)

◆

Flow-Through or Pipelined output mode on either Port via

the FT/PIPE pins

Counter enable and reset features

Dual chip enables allow for depth expansion without

additional logic

◆

Functional Block Diagram

R/WR

R/W

OEL

OER

CE0R

CE1R

CE1⁰L^L

0/1

FT/PIPE

I/O0R - I/O8R

I/O0L - I/O8L

I/O

Control

I/O

Control

(1)

13R

A13L

Counter/

Address

Reg.

Counter/

Address

Reg.

MEMORY

ARRAY

C⁰L^RK

CLK

ADS

CNTEN

CNTRST

ADS

CNTEN

CNTRST

5653 drw 01

NOTE:

1. A¹³is a NC for IDT709159.

AUGUST 2003

DSC-5653/2

12 3 4 5 6 7...16

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IDT709179L9PFI	IDT	获取价格	Dual-Port SRAM, 32KX9, 20ns, CMOS, PQFP100, TQFP-100