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IDT709169L7BFG PDF预览

IDT709169L7BFG

更新时间: 2024-11-05 15:34:43
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
16页 179K
描述
Dual-Port SRAM, 16KX9, 18ns, CMOS, PBGA100, 10 X 10 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FPBGA-100

IDT709169L7BFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:10 X 10 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FPBGA-100针数:100
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:18 ns其他特性:PIPELINED OR FLOW-THROUGH ARCHITECTURE
JESD-30 代码:S-PBGA-B100JESD-609代码:e3
长度:10 mm内存密度:147456 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:9
功能数量:1端子数量:100
字数:16384 words字数代码:16000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:16KX9
封装主体材料:PLASTIC/EPOXY封装代码:LFBGA
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.5 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:10 mm
Base Number Matches:1

IDT709169L7BFG 数据手册

 浏览型号IDT709169L7BFG的Datasheet PDF文件第2页浏览型号IDT709169L7BFG的Datasheet PDF文件第3页浏览型号IDT709169L7BFG的Datasheet PDF文件第4页浏览型号IDT709169L7BFG的Datasheet PDF文件第5页浏览型号IDT709169L7BFG的Datasheet PDF文件第6页浏览型号IDT709169L7BFG的Datasheet PDF文件第7页 
HIGH-SPEED 16/8K x 9  
SYNCHRONOUS PIPELINED  
DUAL-PORT STATIC RAM  
IDT709169/59L  
Features  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial:6.5/7.5/9ns(max.)  
Industrial:7.5ns (max.)  
Full synchronous operation on both ports  
– 3.5ns setup to clock and 0ns hold on all control, data, and  
address inputs  
Data input, address, and control registers  
– Fast 6.5ns clock to data out in the Pipelined output mode  
– Self-timed write allows fast cycle time  
Low-power operation  
IDT709169/59L  
– 10ns cycle time,100MHzoperationinPipelinedoutputmode  
TTL- compatible, single 5V (±10%) power supply  
Industrial temperature range (–40°C to +85°C) is  
available for 83MHz  
Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-  
pin fine pitch Ball Grid Array (fpBGA) packages.  
Active:925mW(typ.)  
Standby: 2.5mW (typ.)  
Flow-Through or Pipelined output mode on either Port via  
the FT/PIPE pins  
Counter enable and reset features  
Dual chip enables allow for depth expansion without  
additional logic  
Functional Block Diagram  
R/WR  
R/W  
L
OEL  
OER  
CE0R  
CE1R  
CE  
CE10LL  
1
0
0/1  
1
0
0/1  
0
0
1
1
0/1  
0/1  
FT/PIPE  
L
FT/PIPE  
R
I/O0R - I/O8R  
I/O0L - I/O8L  
I/O  
Control  
I/O  
Control  
(1)  
(1)  
13R  
A13L  
A
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
MEMORY  
ARRAY  
A
C0LRK  
R
R
A
0L  
CLK  
L
L
ADS  
CNTEN  
CNTRST  
ADS  
CNTEN  
CNTRST  
R
L
R
L
5653 drw 01  
NOTE:  
1. A13 is a NC for IDT709159.  
AUGUST 2003  
1
DSC-5653/2  
©2003IntegratedDeviceTechnology,Inc.  

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