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IDT70825L45PFG PDF预览

IDT70825L45PFG

更新时间: 2024-11-15 06:56:19
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
21页 213K
描述
Standard SRAM, 8KX16, 45ns, CMOS, PQFP80, TQFP-80

IDT70825L45PFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:TQFP-80针数:80
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.83
最长访问时间:45 ns其他特性:AUTOMATIC POWER-DOWN
JESD-30 代码:S-PQFP-G80JESD-609代码:e3
长度:14 mm内存密度:131072 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端子数量:80字数:8192 words
字数代码:8000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8KX16封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mm

IDT70825L45PFG 数据手册

 浏览型号IDT70825L45PFG的Datasheet PDF文件第2页浏览型号IDT70825L45PFG的Datasheet PDF文件第3页浏览型号IDT70825L45PFG的Datasheet PDF文件第4页浏览型号IDT70825L45PFG的Datasheet PDF文件第5页浏览型号IDT70825L45PFG的Datasheet PDF文件第6页浏览型号IDT70825L45PFG的Datasheet PDF文件第7页 
IDT70825S/L  
HIGH SPEED 128K (8K X 16 BIT)  
SEQUENTIAL ACCESS  
RANDOM ACCESS MEMORY (SARAM™)  
Features  
Architecture based on Dual-Port RAM cells  
Compatible with Intel BMIC and 82430 PCI Set  
Width and Depth Expandable  
Sequential side  
High-speed access  
Military: 35/45ns (max.)  
– Commercial: 20/25/35/45ns (max.)  
Low-power operation  
Address based flags for buffer control  
IDT70825S  
– Pointer logic supports up to two internal buffers  
Battery backup operation - 2V data retention  
TTL-compatible, single 5V (+10%) power supply  
Available in 80-pin TQFP and 84-pin PGA  
Military product compliant to MIL-PRF-38535 QML  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
Active: 775mW (typ.)  
Standby: 5mW (typ.)  
IDT70825L  
Active: 775mW (typ.)  
Standby: 1mW (typ.)  
8K x 16 Sequential Access Random Access Memory  
(SARAM )  
– Sequential Access from one port and standard Random  
Access from the other port  
– Separate upper-byte and lower-byte control of the  
Random Access Port  
High speed operation  
– 20ns tAA for random access port  
– 20ns tCD for sequential port  
– 25ns clock cycle time  
Description  
The IDT70825 is a high-speed 8K x 16-Bit Sequential Access  
Random Access Memory (SARAM). The SARAM offers a single-chip  
solution to buffer data sequentially on one port, and be accessed  
randomly (asynchronously) through the other port. The device has a  
Functional Block Diagram  
13  
RST  
SCLK  
CNTEN  
SOE  
SSTRT  
A
0-12  
CE  
OE  
Random  
Access  
Port  
Sequential  
Access  
R/W  
LB LSB  
UB MSB  
CMD  
1
2
Port  
Controls  
SSTRT  
Controls  
,
SCE  
SR/W  
SLD  
8K X 16  
Memory  
Array  
16  
16  
16  
Data  
Addr  
R
Reg.  
13  
Data  
L
I/O0-15  
SI/O0-15  
13  
Addr  
L
R
13  
RST  
13  
Pointer/  
Counter  
13  
13  
Start Address for Buffer #1  
End Address for Buffer #1  
Start Address for Buffer #2  
End Address for Buffer #2  
Flow Control Buffer  
13  
EOB  
1
2
COMPARATOR  
EOB  
Flag Status  
3016 drw 01  
MAY 2000  
1
DSC-3016/9  
©2000IntegratedDeviceTechnology,Inc.  
6.07  

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