Datasheet > IDT7028L

IDT7028L

更新时间： 2024-11-24 23:01:07

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
17页	151K
描述
HIGH-SPEED 64K x 16 DUAL-PORT STATIC RAM

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中文翻译

获取价格

数据手册

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IDT7028L 数据手册

HIGH-SPEED

IDT7028L

64K x 16 DUAL-PORT

STATIC RAM

Features

◆

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Interrupt Flag

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

◆

On-chip port arbitration logic

– Commercial:15/20ns (max.)

Low-power operation

Full on-chip hardware support of semaphore signaling

between ports

– IDT7028L

◆

Fully asynchronous operation from either port

Separate upper-byte and lower-byte controls for multi-

plexed bus and bus matching compatibility

TTL-compatible, single 5V (±10%) power supply

Available in a 100-pin TQFP

Active:1W(typ.)

Standby: 1mW (typ.)

◆

Dual chip enables allow for depth expansion without

external logic

IDT7028 easily expands data bus width to 32 bits or

more using the Master/Slave select when cascading more

than one device

◆

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

FunctionalBlockDiagram

R/WL

UBL

R/WR

UBR

CE0L

CE0R

CE1L

CE1R

OER

LBR

OEL

LBL

I/O ^8-15L

I/O_8-15R

I/O

Control

I/O

Control

0-7L

I/O

I/O0-7R

(1,2)

BUSYR

BUSYL

64Kx16

MEMORY

ARRAY

7028

15L

A15R

Address

Decoder

Address

Decoder

A0L

A_0R

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE0R

CE0L

CE_1L

OEL

CE1R

OER

R/WL

R/WR

SEML

INTL

SEMR

(2)

INTR

M/S⁽²⁾

4836 drw 01

NOTES:

1. BUSY is an input as a Slave (M/S = V^IL) and an output when it is a Master (M/S = VIH).

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

JANUARY 2001

DSC-4836/2

12 3 4 5 6 7...17

中文翻译

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