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IDT7028L15PFG PDF预览

IDT7028L15PFG

更新时间: 2024-10-27 13:02:11
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
17页 151K
描述
Dual-Port SRAM, 64KX16, 15ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100

IDT7028L15PFG 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP,针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.48
Is Samacsys:N最长访问时间:15 ns
JESD-30 代码:S-PQFP-G100JESD-609代码:e3
长度:14 mm内存密度:1048576 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端子数量:100字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX16封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

IDT7028L15PFG 数据手册

 浏览型号IDT7028L15PFG的Datasheet PDF文件第2页浏览型号IDT7028L15PFG的Datasheet PDF文件第3页浏览型号IDT7028L15PFG的Datasheet PDF文件第4页浏览型号IDT7028L15PFG的Datasheet PDF文件第5页浏览型号IDT7028L15PFG的Datasheet PDF文件第6页浏览型号IDT7028L15PFG的Datasheet PDF文件第7页 
HIGH-SPEED  
IDT7028L  
64K x 16 DUAL-PORT  
STATIC RAM  
Features  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
Interrupt Flag  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
On-chip port arbitration logic  
– Commercial:15/20ns (max.)  
Low-power operation  
Full on-chip hardware support of semaphore signaling  
between ports  
IDT7028L  
Fully asynchronous operation from either port  
Separate upper-byte and lower-byte controls for multi-  
plexed bus and bus matching compatibility  
TTL-compatible, single 5V (±10%) power supply  
Available in a 100-pin TQFP  
Active:1W(typ.)  
Standby: 1mW (typ.)  
Dual chip enables allow for depth expansion without  
external logic  
IDT7028 easily expands data bus width to 32 bits or  
more using the Master/Slave select when cascading more  
than one device  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
FunctionalBlockDiagram  
R/WL  
UBL  
R/WR  
UBR  
CE0L  
CE0R  
CE1L  
CE1R  
OER  
LBR  
OEL  
LBL  
I/O 8-15L  
I/O8-15R  
I/O  
Control  
I/O  
Control  
0-7L  
I/O  
I/O0-7R  
(1,2)  
(1,2)  
BUSYR  
BUSYL  
64Kx16  
MEMORY  
ARRAY  
7028  
15L  
A15R  
A
Address  
Decoder  
Address  
Decoder  
A0L  
A0R  
16  
16  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE0R  
CE0L  
CE1L  
OEL  
CE1R  
OER  
R/WL  
R/WR  
SEML  
INTL  
SEMR  
(2)  
(2)  
INTR  
M/S(2)  
4836 drw 01  
NOTES:  
1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH).  
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
JANUARY 2001  
1
DSC-4836/2  
©2000IntegratedDeviceTechnology,Inc.  

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