IDT7024S/L
HIGH-SPEED
4K x 16 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
more than one device
FEATURES:
• M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
• Busy and Interrupt Flags
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Military: 20/25/35/55/70ns (max.)
— Commercial: 15/17/20/25/35/55ns (max.)
• Low-power operation
• Devices are capable of withstanding greater than 2001V
electrostatic discharge.
— IDT7024S
Active: 750mW (typ.)
• Fully asynchronous operation from either port
• Battery backup operation—2V data retention
• TTL-compatible, single 5V (±10%) power supply
• Available in 84-pin PGA, 84-pin quad flatpack, 84-pin
PLCC, and 100-pin Thin Quad Plastic Flatpack
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
Standby: 5mW (typ.)
— IDT7024L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• Separate upper-byte and lower-byte control for
multiplexed bus compatibility
• IDT7024 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
FUNCTIONAL BLOCK DIAGRAM
R/
UB
W
L
L
R/
W
R
UB
R
LB
CE
OE
L
LB
CE
OER
R
L
R
L
I/O8L-I/O15L
I/O0L-I/O7L
I/O8R-I/O15R
I/O0R-I/O7R
I/O
Control
I/O
Control
BUSY(1,2)
L
BUSY (1,2)
R
A
11L
0L
A
11R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
A
0R
12
12
NOTES:
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
1. (MASTER):
BUSY is output;
(SLAVE): BUSY
is input.
CE
OE
R/
L
CE
OE
R/
R
L
R
WL
W
R
2. BUSY outputs
and INT outputs
are non-tri-stated
push-pull.
SEM
R
SEM
L
INT(2)
L
INT (2)
R
M/
S
2740 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OCTOBER 1996
©1996 Integrated Device Technology, Inc.
DSC-2740/6
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
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