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IDT7024S35JGB PDF预览

IDT7024S35JGB

更新时间: 2024-12-01 12:58:51
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
20页 291K
描述
Dual-Port SRAM, 4KX16, 35ns, CMOS, PQCC84, 1.150 X 1.150 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-84

IDT7024S35JGB 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:LCC
包装说明:QCCJ, LDCC84,1.2SQ针数:84
Reach Compliance Code:compliantECCN代码:3A001.A.2.C
HTS代码:8542.32.00.41风险等级:5.06
最长访问时间:35 nsI/O 类型:COMMON
JESD-30 代码:S-PQCC-J84JESD-609代码:e3
长度:29.3116 mm内存密度:65536 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端口数量:2端子数量:84
字数:4096 words字数代码:4000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:4KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC84,1.2SQ
封装形状:SQUARE封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
筛选级别:MIL-PRF-38535 Class B座面最大高度:4.572 mm
最大待机电流:0.00003 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.3 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Matte Tin (Sn) - annealed端子形式:J BEND
端子节距:2.54 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:29.3116 mm
Base Number Matches:1

IDT7024S35JGB 数据手册

 浏览型号IDT7024S35JGB的Datasheet PDF文件第2页浏览型号IDT7024S35JGB的Datasheet PDF文件第3页浏览型号IDT7024S35JGB的Datasheet PDF文件第4页浏览型号IDT7024S35JGB的Datasheet PDF文件第5页浏览型号IDT7024S35JGB的Datasheet PDF文件第6页浏览型号IDT7024S35JGB的Datasheet PDF文件第7页 
IDT7024S/L  
HIGH-SPEED  
4K x 16 DUAL-PORT  
STATIC RAM  
Integrated Device Technology, Inc.  
more than one device  
FEATURES:  
• M/S = H for BUSY output flag on Master  
M/S = L for BUSY input on Slave  
• Busy and Interrupt Flags  
• On-chip port arbitration logic  
• Full on-chip hardware support of semaphore signaling  
between ports  
• True Dual-Ported memory cells which allow simulta-  
neous access of the same memory location  
• High-speed access  
— Military: 20/25/35/55/70ns (max.)  
— Commercial: 15/17/20/25/35/55ns (max.)  
• Low-power operation  
• Devices are capable of withstanding greater than 2001V  
electrostatic discharge.  
— IDT7024S  
Active: 750mW (typ.)  
• Fully asynchronous operation from either port  
• Battery backup operation—2V data retention  
• TTL-compatible, single 5V (±10%) power supply  
• Available in 84-pin PGA, 84-pin quad flatpack, 84-pin  
PLCC, and 100-pin Thin Quad Plastic Flatpack  
• Industrial temperature range (–40°C to +85°C) is avail-  
able, tested to military electrical specifications  
Standby: 5mW (typ.)  
— IDT7024L  
Active: 750mW (typ.)  
Standby: 1mW (typ.)  
• Separate upper-byte and lower-byte control for  
multiplexed bus compatibility  
• IDT7024 easily expands data bus width to 32 bits or  
more using the Master/Slave select when cascading  
FUNCTIONAL BLOCK DIAGRAM  
R/  
UB  
W
L
L
R/  
W
R
UB  
R
LB  
CE  
OE  
L
LB  
CE  
OER  
R
L
R
L
I/O8L-I/O15L  
I/O0L-I/O7L  
I/O8R-I/O15R  
I/O0R-I/O7R  
I/O  
Control  
I/O  
Control  
BUSY(1,2)  
L
BUSY (1,2)  
R
A
11L  
0L  
A
11R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
A
0R  
12  
12  
NOTES:  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
1. (MASTER):  
BUSY is output;  
(SLAVE): BUSY  
is input.  
CE  
OE  
R/  
L
CE  
OE  
R/  
R
L
R
WL  
W
R
2. BUSY outputs  
and INT outputs  
are non-tri-stated  
push-pull.  
SEM  
R
SEM  
L
INT(2)  
L
INT (2)  
R
M/  
S
2740 drw 01  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
OCTOBER 1996  
©1996 Integrated Device Technology, Inc.  
DSC-2740/6  
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.  
1
6.15  

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