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IDT23S09-1DCI PDF预览

IDT23S09-1DCI

更新时间: 2024-11-19 22:23:03
品牌 Logo 应用领域
艾迪悌 - IDT 时钟
页数 文件大小 规格书
8页 57K
描述
IDT23S09 3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE

IDT23S09-1DCI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:16
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.67系列:23S
输入调节:STANDARDJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:9.9314 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.008 A
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:16
实输出次数:8最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
电源:3.3 V传播延迟(tpd):8.7 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.25 ns
座面最大高度:1.7272 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:3.937 mm最小 fmax:133 MHz
Base Number Matches:1

IDT23S09-1DCI 数据手册

 浏览型号IDT23S09-1DCI的Datasheet PDF文件第2页浏览型号IDT23S09-1DCI的Datasheet PDF文件第3页浏览型号IDT23S09-1DCI的Datasheet PDF文件第4页浏览型号IDT23S09-1DCI的Datasheet PDF文件第5页浏览型号IDT23S09-1DCI的Datasheet PDF文件第6页浏览型号IDT23S09-1DCI的Datasheet PDF文件第7页 
IDT23S09  
3.3V ZERO DELAY  
CLOCK BUFFER, SPREAD  
SPECTRUM COMPATIBLE  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution  
• 10MHz to 133MHz operating frequency  
• Distributes one clock input to one bank of five and one bank of  
four outputs  
The IDT23S09 is a high-speed phase-lock loop (PLL) clock buffer,  
designedtoaddresshigh-speedclockdistributionapplications. Thezero  
delay is achieved by aligning the phase between the incoming clock and  
the output clock, operable within the range of 10 to 133MHz.  
• Separate output enable for each output bank  
• Output Skew < 250ps  
• Low jitter <200 ps cycle-to-cycle  
• IDT23S09-1 for Standard Drive  
• IDT23S09-1H for High Drive  
The IDT23S09 is a 16-pin version of the IDT23S05. The IDT23S09  
acceptsonereferenceinput,anddrivestwobanksoffourlowskewclocks.  
The-1Hversionofthisdeviceoperatesupto133MHzfrequencyandhas  
higher drive than the -1 device. All parts have on-chip PLLs which lock  
to an input clock on the REF pin. The PLL feedback is on-chip and is  
obtained from the CLKOUT pad. In the absence of an input clock, the  
IDT23S09enterspowerdown. Inthismode,thedevicewilldrawlessthan  
• No external RC network required  
• Operates at 3.3V VDD  
• Spread spectrum compatible  
• Available in SOIC and TSSOP packages  
12µAforCommercialTemperaturerangeandlessthan2AforIndustrial  
temperature range, and the outputs are tri-stated.  
The IDT23S09 is characterized for both Industrial and Commercial  
operation.  
FUNCTIONALBLOCKDIAGRAM  
16  
CLKOUT  
2
CLKA1  
PLL  
1
REF  
3
CLKA2  
14  
CLKA3  
15  
CLKA4  
8
S2  
Control  
Logic  
9
S1  
6
CLKB1  
7
CLKB2  
10  
CLKB3  
11  
CLKB4  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
OCTOBER 2003  
1
c
2003 Integrated Device Technology, Inc.  
DSC - 6395/3  

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