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IDT23S09-1HDC8 PDF预览

IDT23S09-1HDC8

更新时间: 2024-10-04 19:20:51
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
8页 71K
描述
PLL Based Clock Driver, 23S Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, SOIC-16

IDT23S09-1HDC8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.64
系列:23S输入调节:STANDARD
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:9.9314 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.012 A湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:16实输出次数:8
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:3.3 V传播延迟(tpd):8.7 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.25 ns
座面最大高度:1.7272 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.937 mm
最小 fmax:133 MHzBase Number Matches:1

IDT23S09-1HDC8 数据手册

 浏览型号IDT23S09-1HDC8的Datasheet PDF文件第2页浏览型号IDT23S09-1HDC8的Datasheet PDF文件第3页浏览型号IDT23S09-1HDC8的Datasheet PDF文件第4页浏览型号IDT23S09-1HDC8的Datasheet PDF文件第5页浏览型号IDT23S09-1HDC8的Datasheet PDF文件第6页浏览型号IDT23S09-1HDC8的Datasheet PDF文件第7页 
IDT23S09  
3.3V ZERO DELAY  
CLOCK BUFFER, SPREAD  
SPECTRUM COMPATIBLE  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution  
• 10MHz to 133MHz operating frequency  
• Distributes one clock input to one bank of five and one bank of  
four outputs  
The IDT23S09 is a high-speed phase-lock loop (PLL) clock buffer,  
designedtoaddresshigh-speedclockdistributionapplications. Thezero  
delay is achieved by aligning the phase between the incoming clock and  
the output clock, operable within the range of 10 to 133MHz.  
• Separate output enable for each output bank  
• Output Skew < 250ps  
• Low jitter <200 ps cycle-to-cycle  
• IDT23S09-1 for Standard Drive  
• IDT23S09-1H for High Drive  
The IDT23S09 is a 16-pin version of the IDT23S05. The IDT23S09  
acceptsonereferenceinput,anddrivestwobanksoffourlowskewclocks.  
The-1Hversionofthisdeviceoperatesupto133MHzfrequencyandhas  
higher drive than the -1 device. All parts have on-chip PLLs which lock  
to an input clock on the REF pin. The PLL feedback is on-chip and is  
obtained from the CLKOUT pad. In the absence of an input clock, the  
IDT23S09enterspowerdown. Inthismode,thedevicewilldrawlessthan  
• No external RC network required  
• Operates at 3.3V VDD  
• Spread spectrum compatible  
• Available in SOIC and TSSOP packages  
12µAforCommercialTemperaturerangeandlessthan2AforIndustrial  
temperature range, and the outputs are tri-stated.  
The IDT23S09 is characterized for both Industrial and Commercial  
operation.  
NOTE: EOL for non-green parts to occur on 5/13/10 per  
PDNU-09-01  
FUNCTIONALBLOCKDIAGRAM  
16  
CLKOUT  
2
CLKA1  
PLL  
1
REF  
3
CLKA2  
14  
CLKA3  
15  
CLKA4  
8
S2  
Control  
Logic  
9
S1  
6
CLKB1  
7
CLKB2  
10  
CLKB3  
11  
CLKB4  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
AUGUST 2009  
1
c
2006 Integrated Device Technology, Inc.  
DSC - 6395/8  

IDT23S09-1HDC8 替代型号

型号 品牌 替代类型 描述 数据表
23S09-1HDCG8 IDT

完全替代

3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE

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