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IDT10490S12Y PDF预览

IDT10490S12Y

更新时间: 2024-02-05 05:12:30
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
7页 81K
描述
Standard SRAM, 64KX1, 12ns, PDSO24

IDT10490S12Y 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.92
Is Samacsys:N最长访问时间:12 ns
I/O 类型:SEPARATEJESD-30 代码:R-PDSO-J24
JESD-609代码:e0内存密度:65536 bit
内存集成电路类型:STANDARD SRAM内存宽度:1
湿度敏感等级:3负电源额定电压:-5.2 V
功能数量:1端子数量:24
字数:65536 words字数代码:64000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64KX1
输出特性:OPEN-EMITTER封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装等效代码:SOJ24,.34
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL电源:-5.2 V
认证状态:Not Qualified子类别:SRAMs
最大压摆率:0.17 mA表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

IDT10490S12Y 数据手册

 浏览型号IDT10490S12Y的Datasheet PDF文件第2页浏览型号IDT10490S12Y的Datasheet PDF文件第3页浏览型号IDT10490S12Y的Datasheet PDF文件第4页浏览型号IDT10490S12Y的Datasheet PDF文件第5页浏览型号IDT10490S12Y的Datasheet PDF文件第6页浏览型号IDT10490S12Y的Datasheet PDF文件第7页 
HIGH-SPEED BiCMOS  
ECL STATIC RAM  
64K (64K x 1-BIT) SRAM  
IDT10490  
IDT100490  
IDT101490  
Integrated Device Technology, Inc.  
FEATURES:  
DESCRIPTION:  
• 65,536 x 1-bit organization  
The IDT10490, IDT100490 and IDT101490 are 65,536-bit  
high-speed BiCMOS ECL static random access memories  
organized as 64K x 1, with separate data input and output. All  
I/Os are fully compatible with ECL levels.  
• Address access time: 7/8/10/12/15 ns  
• Low power dissipation: 500mW (typ.)  
• Guaranteed Output Hold time  
• Fully compatible with ECL logic levels  
• Separate data input and output  
• JEDEC standard through-hole package  
• Guaranteed-performance die available for MCMs/hybrids  
Thesedevicesarepartofa familyofasynchronousone-bit-  
wide ECL SRAMs. The device has been configured to follow  
the standard ECL SRAM JEDEC pinout. Because they are  
manufactured in BiCMOS technology, power dissipation is  
greatly reduced over equivalent bipolar devices.  
The fast access time and guaranteed Output Hold time  
allowgreatermarginforsystemtimingvariation. DataINsetup  
time specified with respect to the trailing edge of Write Pulse  
eases write timing allowing balanced Read and Write cycle  
times.  
FUNCTIONAL BLOCK DIAGRAM  
A0  
16,384-BIT  
MEMORY  
ARRAY  
VCC  
VEE  
DECODER  
A15  
SENSE AMPS  
AND READ/WRITE  
CONTROL  
D0  
Q0  
WE  
CS  
2757 drw 01  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
COMMERCIAL TEMPERATURE RANGE  
SEPTEMBER 1992  
1992 Integrated Device Technology, Inc.  
DSC-8001/4  
1

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