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ICSLV810SILF PDF预览

ICSLV810SILF

更新时间: 2024-11-13 14:42:43
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
13页 241K
描述
Low Skew Clock Driver, 810 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, 0.300 INCH, SOIC-20

ICSLV810SILF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.38系列:810
输入调节:STANDARDJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:12.8 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER功能数量:1
反相输出次数:端子数量:20
实输出次数:10最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
传播延迟(tpd):3.5 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.2 ns座面最大高度:2.65 mm
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):1.425 V
标称供电电压 (Vsup):1.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
最小 fmax:170 MHzBase Number Matches:1

ICSLV810SILF 数据手册

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ICSLV810  
Buffer/Clock Driver  
Description  
Features  
The ICSLV810 is a low skew 1.5 V to 2.5 V, 1:10 fanout  
buffer. This device is specifically designed for data  
communications clock management. The large fanout  
from a single input line reduces loading on the input  
clock. The TTL level outputs reduce noise levels on the  
part. Typical applications are clock and signal  
distribution.  
Packaged in 20-pin SOIC/QSOP/SSOP  
Split 1:10 fanout Buffer  
Maximum skew between outputs of different  
packages 0.75 ns  
Max propagation delay of 3.8 ns  
Operating voltage of 2.5 V on Bank A  
Operating voltage of 1.5 V to 2.5 V on Banks B and C  
Advanced, low power, CMOS process  
Industrial temperature range -40° C to +85° C  
3.3 V tolerant input  
Block Diagram  
VDDA  
CLK 1  
CLK 2  
CLK 3  
CLK 4  
CLK 5  
CLKIN  
CLK 6  
CLK 7  
CLK 8  
CLK 9  
CLK 10  
VDDB  
VDDC  
MDS LV810 D  
1
Revision 062105  
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com  

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