Integrated
Circuit
Systems, Inc.
ICS952003
Preliminary Product Review
Programmable Timing Control Hub™ for P4™ processor
Recommended Application:
Pin Configuration
SIS 645/650 style chipsets.
VDDREF
**FS0/REF0
**FS1/REF1
**FS2/REF2
GNDREF
X1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDSD
SDRAM
GNDSD
Output Features:
CPU_STOP#*
CPUCLKT_1
CPUCLKC_1
VDDCPU
GNDCPU
CPUCLKT_0
CPUCLKC_0
IREF
GNDA
VDDA
SCLK
SDATA
PD#*/Vtt_PWRGD
GNDAGP
AGPCLK0
AGPCLK1
VDDAGP
VDDA48
48MHz
24_48MHz/MULTISEL*
GND48
•
2 - Pairs of differential CPUCLKs (differential current mode)
•
•
1 - SDRAM @ 3.3V
8 - PCI @3.3V
X2
GNDZ
ZCLK0
ZCLK1
•
•
•
•
2 - AGP @ 3.3V
VDDZ
*PCI_STOP#
VDDPCI
2 - ZCLKs @ 3.3V
1- 48MHz, @3.3V fixed.
1- 24/48MHz, @3.3V selectable by I2C
(Default is 24MHz)
**FS3/PCICLK_F0
**FS4/PCICLK_F1
PCICLK0
PCICLK1
GNDPCI
VDDPCI
•
3- REF @3.3V, 14.318MHz.
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GNDPCI
Features/Benefits:
•
Selectable asynchronous/synchronous SDRAM, AGP,
ZCLK and PCI outputs
48-Pin 300-mil SSOP
•
Programmable output frequency, divider ratios, output rise/
falltime, output skew.
* These inputs have a 120K pull up to VDD.
** These inputs have a 120K pull down to GND.
•
•
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
•
•
Programmable watch dog safe frequency.
Block Diagram
Support I2C Index read/write and block read/write
operations.
•
•
•
For PC133 SDRAM system use the ICS9179-16 as the
memory buffer.
For DDR SDRAM system use the ICS93705 or
ICS93722 as the memory buffer.
PLL2
48MHz
24_48MHz
/ 2
X1
X2
XTAL
OSC
REF (1:0)
2
Uses external 14.318MHz crystal.
Key Specifications:
PLL1
Spread
Spectrum
CPU
DIVDER
CPUCLKT (1:0)
CPUCLKC (1:0)
Stop
2
•
•
•
PCI - PCI output skew: < 500ps
CPU - SDRAM output skew: < 1ns
AGP - AGP output skew: <150ps
2
ZCLK
DIVDER
ZCLK (1:0)
2
6
Control
Logic
Functionality
SDATA
SCLK
FS (4:0)
PCI
DIVDER
Stop
PCICLK (9:0)
PCICLK_F (1:0)
AGP (1:0)
Bit 2 Bit 7 Bit 6 Bit 5 Bit 4 CPU SDRAM ZCLK
AGP
PCI
FS4 FS3 FS2 FS1 FS0 (MHz) (MHz) (MHz) (MHz)
(MHz)
33.33
33.33
33.33
33.33
30.00
31.25
33.33
33.33
33.33
31.25
41.67
33.33
33.33
31.67
31.67
25.00
2
2
PD#
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AGP
DIVDER
66.67
66.67 66.67
66.67
66.67
66.67
66.67
60.00
62.50
66.67
66.67
66.67
62.50
83.33
66.67
66.67
63.33
63.33
50.00
PCI_STOP#
CPU_STOP#
MULTISEL
PD#/Vtt_PWRGD
100.00 100.00 66.67
100.00 200.00 66.67
100.00 133.33 66.67
100.00 150.00 60.00
100.00 125.00 62.50
100.00 160.00 66.67
100.00 133.33 80.00
100.00 200.00 66.67
100.00 166.67 62.50
100.00 166.67 71.43
80.00 133.33 66.67
80.00 133.33 66.67
Config.
Reg.
SDRAM
DIVDER
SDRAM
I REF
Power Groups
VDDCPU = CPU
VDDPCI = PCICLK_F, PCICLK
VDDSD = SDRAM
95.00
95.00 126.67 63.33
66.67 66.67 50.00
95.00 63.33
AVDD48 = 48MHz, 24MHz, fixed PLL
AVDD = Analog Core PLL
VDDAGP= AGP
Note: For additional margin testing frequencies, refer to Byte 4
VDDREF = Xtal, REF
VDDZ = ZCLK
0488B—04/09/02
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to
changewithoutnotice.