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ICS952601 PDF预览

ICS952601

更新时间: 2024-11-21 11:14:51
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
25页 228K
描述
Programmable Timing Control HubTM for Next Gen P4TM Processor

ICS952601 数据手册

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DATASHEET  
Programmable Timing Control HubTM for Next  
Gen P4TM Processor  
ICS952601  
Features/Benefits:  
Recommended Application:  
Supports tight ppm accuracy clocks for Serial-ATA.  
Supports spread spectrum modulation, 0 to -0.5%  
down spread.  
CK409 clock, Intel Yellow Cover part  
Output Features:  
3 - 0.7V current-mode differential CPU pairs  
1 - 0.7V current-mode differential SRC pair  
7 - PCI (33MHz)  
3 - PCICLK_F, (33MHz) free-running  
1 - USB, 48MHz  
1 - DOT, 48MHz  
2 - REF, 14.318MHz  
4 - 3V66, 66.66MHz  
1 - VCH/3V66, selectable 48MHz or 66MHz  
Supports CPU clks up to 400MHz in test mode.  
Uses external 14.318MHz crystal, external crystal load  
caps are required for frequency tuning.  
Supports undriven differential CPU, SRC pair in PD#  
and CPU_STOP# for power management.  
Pin Configuration  
Key Specifications:  
REF0  
1
2
3
4
5
56 FS_B  
55 VDDA  
54 GNDA  
53 GND  
52 IREF  
CPU/SRC outputs cycle-cycle jitter < 125ps  
3V66 outputs cycle-cycle jitter < 250ps  
PCI outputs cycle-cycle jitter < 250ps  
CPU outputs skew: < 100ps  
REF1  
VDDREF  
X1  
X2  
GND  
+/- 300ppm frequency accuracy on CPU & SRC clocks  
6
51 FS_A  
7
8
9
50 CPU_STOP#  
49 PCI_STOP#  
48  
VDDCPU  
47 CPUCLKT2  
46 CPUCLKC2  
PCICLK_F0  
PCICLK_F1  
PCICLK_F2  
VDDPCI  
GND  
Functionality  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
CPU  
B6b5 FS_A FS_B MHz  
SRC  
MHz  
3V66 PCI  
MHz MHz  
REF USB/DOT  
MHz  
MHz  
48.00  
Ref/N5  
48.00  
48.00  
48.00  
Hi-Z  
45  
PCICLK0  
PCICLK1  
PCICLK2  
PCICLK3  
VDDPCI  
GND  
PCICLK4  
PCICLK5  
PCICLK6  
GND  
0
0
0
1
1
1
0
0
1
1
0
100 100/200 66.66 33.33 14.318  
44 CPUCLKT1  
43 CPUCLKC1  
MID Ref/N0 Ref/N1 Ref/N2 Ref/N3 Ref/N4  
1
0
1
200 100/200 66.66 33.33 14.318  
133 100/200 66.66 33.33 14.318  
166 100/200 66.66 33.33 14.318  
0
1
42  
VDDCPU  
41 CPUCLKT0  
40 CPUCLKC0  
39 GND  
MID Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
0
1
0
1
200 100/200 66.66 33.33 14.318  
400 100/200 66.66 33.33 14.318  
266 100/200 66.66 33.33 14.318  
333 100/200 66.66 33.33 14.318  
48.00  
48.00  
48.00  
48.00  
38  
37  
SRCCLKT  
SRCCLKC  
PD# 21  
36 VDD  
22  
23  
24  
25  
26  
27  
28  
35 Vtt_PWRGD#  
3V66_0  
3V66_1  
VDD3V66  
GND  
3V66_2  
3V66_3  
SCLK  
34  
VDD48  
33 GND  
32  
31  
30  
29  
48MHz_DOT  
48MHz_USB  
SDATA  
3V66_4/VCH  
56-pin SSOP & TSSOP  
IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor  
701J—01/25/10  
1

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