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ICS9248AG-192LF-T PDF预览

ICS9248AG-192LF-T

更新时间: 2024-11-11 15:42:19
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
15页 201K
描述
66.6MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28, 4.40 MM, 0.65 MM PITCH, GREEN, MO-153, TSSOP-28

ICS9248AG-192LF-T 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP28,.25针数:28
Reach Compliance Code:compliant风险等级:5.73
Is Samacsys:NJESD-30 代码:R-PDSO-G28
JESD-609代码:e3长度:9.7 mm
端子数量:28最高工作温度:70 °C
最低工作温度:最大输出时钟频率:66.6 MHz
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP28,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:2.5,3.3 V主时钟/晶体标称频率:14.318 MHz
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Clock Generators最大压摆率:80 mA
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

ICS9248AG-192LF-T 数据手册

 浏览型号ICS9248AG-192LF-T的Datasheet PDF文件第2页浏览型号ICS9248AG-192LF-T的Datasheet PDF文件第3页浏览型号ICS9248AG-192LF-T的Datasheet PDF文件第4页浏览型号ICS9248AG-192LF-T的Datasheet PDF文件第5页浏览型号ICS9248AG-192LF-T的Datasheet PDF文件第6页浏览型号ICS9248AG-192LF-T的Datasheet PDF文件第7页 
ICS9248-192  
Integrated  
Circuit  
Systems,Inc.  
Frequency Timing Generator for Transmeta Systems  
Pin Configuration  
RecommendedApplication:  
Transmeta  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
GNDREF  
X1  
VDDREF  
REF  
CPU_STOP#  
VDDLCPU  
GNDLCPU  
CPUCLK0  
PCI_STOP#  
GND_Core  
VDD_Core  
SEL66/60#  
VDD48  
GND48  
48MHz/CPU3.3v_2.5V#sel  
24-48MHz/Sel48_24#  
OutputFeatures:  
X2  
PD#  
1CPU(2.5V or 3.3V selectable) up to 66.6MHz &  
overclocking of 66MHz.  
PCICLK0  
PCICLK1  
PCICLK2  
GNDPCI  
VDDPCI  
PCICLK3  
PCICLK4  
PCICLK5  
SDATA  
SCLK  
6 PCI (3.3V) @ 33.3MHz (all are free running  
selectable).  
1 REF (3.3V) at 14.318MHz.  
1 48MHz (3.3V).  
1 24_48MHz selectable output.  
Features:  
Supports Spread Spectrum modulation for CPU and  
28-Pin TSSOP  
PCI clocks, default -0.4 downspread.  
Efficient Power management scheme through stop  
clocks and power down modes.  
Uses external 14.318MHz crystal, no external load  
cap required for CL=18pF crystal.  
28-pin TSSOP package, 4.40mm (173mil).  
SkewCharacteristics:  
CPU – CPU <175ps  
PCI – PCI < 500ps  
CPU(early) – PCI = 1.5ns – 4ns.  
Block Diagram  
PLL2  
48MHz  
24_48MHz  
/ 2  
X1  
X2  
XTAL  
OSC  
REF  
PLL1  
Spread  
CPU  
DIVDER  
Stop  
CPUCLK0  
Spectrum  
SEL48_24#  
CPU3.3V_2.5V#sel  
SEL66/60#  
PD#  
Control  
Logic  
PCI  
DIVDER  
Stop  
PCICLK (5:0)  
6
PCI_STOP#  
CPU_STOP#  
SDATA  
Power Groups  
Config.  
Reg.  
VDD_Core, GND_Core = PLL core  
VDDREF, GNDREF = REF, X1, X2  
VDDPCI, GNDPCI = PCICLK (5:0)  
VDD48, GND48 = 48MHz (1:0)  
SCLK  
0540F—10/27/05  

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