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ICS844003AGI-01LFT PDF预览

ICS844003AGI-01LFT

更新时间: 2024-11-04 19:45:35
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
14页 265K
描述
Clock Generator, 680MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24

ICS844003AGI-01LFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.32
JESD-30 代码:R-PDSO-G24JESD-609代码:e3
长度:7.8 mm湿度敏感等级:1
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:680 MHz
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260主时钟/晶体标称频率:27.2 MHz
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

ICS844003AGI-01LFT 数据手册

 浏览型号ICS844003AGI-01LFT的Datasheet PDF文件第2页浏览型号ICS844003AGI-01LFT的Datasheet PDF文件第3页浏览型号ICS844003AGI-01LFT的Datasheet PDF文件第4页浏览型号ICS844003AGI-01LFT的Datasheet PDF文件第5页浏览型号ICS844003AGI-01LFT的Datasheet PDF文件第6页浏览型号ICS844003AGI-01LFT的Datasheet PDF文件第7页 
ICS844003I-01  
FEMTOCLOCKS™ C RYSTAL-TO-LVDS  
FREQUENCY SYNTHESIZER  
Integrated  
Circuit  
Systems, Inc.  
GENERAL DESCRIPTION  
FEATURES  
The ICS844003I-01 is a 3 differential output  
• Three LVDS outputs on two banks, Bank A with one  
LVDS pair and Bank B with 2 LVDS output pairs  
ICS  
LVDS Synthesizer designed to generate  
Ethernet reference clock frequencies and is a  
member of the HiPerClocks™ family of high  
performance clock solutions from ICS. Using a  
HiPerClockS™  
• Using a 19.53125MHz or 25MHz crystal, the two output  
banks can be independently set for 625MHz, 312.5MHz,  
156.25MHz or 125MHz  
19.53125MHz or 25MHz, 18pF parallel resonant crystal,  
the following frequencies can be generated based on the  
settings of 4 frequency select pins (DIV_SELA[1:0],  
DIV_SELVB[1:0]): 625MHz, 312.5MHz, 156.25MHz, and  
125MHz. The 844003I-01 has 2 output banks, Bank A with  
1 differential LVDS output pair and Bank B with 2 differen-  
tial LVDS output pairs. To guarantee operation at 85°C,  
only 1 bank should be enabled at any given time. Do not  
enable Bank A and Bank B at the same time.  
• Selectable crystal oscillator interface or LVCMOS/LVTTL  
single-ended input  
• VCO range: 490MHz to 680MHz  
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):  
0.56ps (typical)  
• 3.3V output supply mode  
• -40°C to 85°C ambient operating temperature (only 1  
bank enabled)  
The two banks have their own dedicated frequency select  
pins and can be independently set for the frequencies men-  
tioned above. The ICS844003I-01 uses ICS’ 3rd genera-  
tion low phase noise VCO technology and can achieve 1ps  
or lower typical rms phase jitter, easily meeting Ethernet  
jitter requirements. The ICS844003I-01 is packaged in a  
small 24-pin TSSOP package.  
• Available in both standard and lead-free RoHS-compliant  
packages  
PIN ASSIGNMENT  
1
2
3
DIV_SELB0  
VCO_SEL  
MR  
24  
23  
22  
DIV_SELB1  
VDDO_B  
QB0  
4
5
6
7
VDDO_A  
nQB0  
21  
20  
19  
18  
17  
16  
15  
14  
13  
QA0  
nQA0  
OEB  
OEA  
FB_DIV  
QB1  
nQB1  
XTAL_SEL  
REF_CLK  
XTAL_IN  
XTAL_OUT  
GND  
8
9
10  
11  
12  
VDDA  
VDD  
DIV_SELA1  
DIV_SELA0  
ICS844003I-01  
24-LeadTSSOP  
BLOCK DIAGRAM  
4.40mm x 7.8mm x 0.92mm  
Pullup  
OEA  
package body  
G Package  
TopView  
Pullup  
DIV_SELA[1:0]  
Pullup  
VCO_SEL  
QA0  
0 0 ÷1  
nQA0  
Pulldown  
0 1 ÷2  
REF_CLK  
XTAL_IN  
0
1
0
1
1 0 ÷3  
1 1 ÷4 (default)  
Phase  
Detector  
VCO  
OSC  
XTAL_OUT  
XTAL_SEL  
QB0  
Pullup  
FB_DIV  
0 0 ÷2  
nQB0  
0 1 ÷4  
0 = ÷25 (default)  
1 = ÷32  
1 0 ÷5  
QB1  
1 1 ÷8 (default)  
Pulldown  
Pullup  
FB_DIV  
DIV_SELB[1:0]  
MR  
nQB1  
Pulldown  
Pullup  
OEB  
844003AGI-01  
www.icst.com/products/hiperclocks.html  
REV.A FEBRUARY 22, 2006  
1

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