Datasheet > ICS844003AGILF

ICS844003AGILF

更新时间： 2024-10-01 11:14:39

品牌	Logo	应用领域
矽成 - ICSI		/
页数	文件大小	规格书
13页	192K
描述
FEMTOCLOCKS? CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

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中文翻译

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数据手册

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ICS844003AGILF 数据手册

PRELIMINARY

ICS844003I

Integrated

Circuit

Systems, Inc.

FEMTOCLOCKS™ C RYSTAL-TO-LVDS

FREQUENCY SYNTHESIZER

GENERAL DESCRIPTION

FEATURES

The ICS844003I is a 3 differential output LVDS

• Three LVDS outputs on two banks, A Bank with one LVDS

pair and B Bank with 2 LVDS output pairs

ICS

HiPerClockS™

Synthesizer designed to generate Ethernet refer-

ence clock frequencies and is a member of the

HiPerClocks™family of high performance clock

solutions from ICS. Using a 31.25MHz or

• Using a 31.25MHz or 26.041666MHz crystal, the two

output banks can be independently set for 625MHz,

312.5MHz, 156.25MHz or 125MHz

26.041666MHz, 18pF parallel resonant crystal, the following

frequencies can be generated based on the settings of 4 fre-

quency select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]):

625MHz, 312.5MHz, 156.25MHz, and 125MHz. The 844003I

has 2 output banks, Bank A with 1 differential LVDS output

pair and Bank B with 2 differential LVDS output pairs.

• Selectable crystal oscillator interface or LVCMOS/LVTTL

single-ended input

• VCO range: 560MHz to 700MHz

• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):

0.63ps (typical)

The two banks have their own dedicated frequency se- • 3.3V output supply mode

lect pins and can be independently set for the frequen-

• -40°C to 85°C ambient operating temperature

cies mentioned above. The ICS844003I uses ICS’ 3rd gen-

eration low phase noise VCO technology and can achieve

1ps or lower typical rms phase jitter, easily meeting

Ethernet jitter requirements. The ICS844003I is packaged

in a small 24-pin TSSOP package.

• Available in both standard and lead-free RoHS-compliant

packages

PIN ASSIGNMENT

DIV_SELB0

VCO_SEL

DIV_SELB1

V^DDO_B

QB0

V^DDO_A

nQB0

QA0

nQA0

CLK_ENB

CLK_ENA

FB_DIV

QB1

nQB1

XTAL_SEL

TEST_CLK

XTAL_IN

XTAL_OUT

GND

V^DDA

VDD

DIV_SELA1

DIV_SELA0

ICS844003I

24-LeadTSSOP

4.40mm x 7.8mm x 0.92mm

package body

BLOCK DIAGRAM

Pullup

CLK_ENA

DIV_SELA[1:0]

G Package

Pullup

VCO_SEL

TopView

QA0

0 0 ÷1

nQA0

Pulldown

0 1 ÷2 (default)

1 0 ÷4

TEST_CLK

XTAL_IN

1 1 ÷5

Phase

Detector

VCO

560-700MHz

OSC

XTAL_OUT

XTAL_SEL

QB0

Pullup

FB_DIV

0 0 ÷1

nQB0

0 1 ÷2

0 = ÷20 (default)

1 = ÷24

1 0 ÷4 (default)

1 1 ÷5

QB1

Pulldown

FB_DIV

DIV_SELB[1:0]

nQB1

Pulldown

Pullup

CLK_ENB

The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial

product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.

844003AGI

www.icst.com/products/hiperclocks.html

REV.B AUGUST 25, 2005

12 3 4 5 6 7...13

中文翻译

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与ICS844003AGILF相关器件

型号	品牌	获取价格	描述	数据表
ICS844003AGILFT	IDT	获取价格	Clock Generator, 700MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, T
ICS844003AGIT	ICSI	获取价格	FEMTOCLOCKS? CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
ICS844003AGITLF	ICSI	获取价格	FEMTOCLOCKS? CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
ICS844003AGLF	IDT	获取价格	Clock Generator, 700MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, T
ICS844003AGLFT	IDT	获取价格	Clock Generator, 700MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, T
ICS844003AGT	IDT	获取价格	Clock Generator, 700MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24
ICS844003AGTLF	IDT	获取价格	Clock Generator, 700MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, T
ICS844003AI01	ICSI	获取价格	FEMTOCLOCKS? CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
ICS844003BG-01LF	IDT	获取价格	Clock Generator, 680MHz, PDSO24, 4.40 X 7.80 MM, 0.92MM HEIGHT, ROHS COMPLIANT, MO-153, TS
ICS844003BGI-01LF	IDT	获取价格	Clock Generator, 680MHz, PDSO24, 4.40 X 7.80 MM, 0.92MM HEIGHT, ROHS COMPLIANT, TSSOP-24

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