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ICS844003AGTLF PDF预览

ICS844003AGTLF

更新时间： 2024-11-04 14:51:19
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
16页 225K
描述
Clock Generator, 700MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24

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ICS844003AGTLF 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：24
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.77
Is Samacsys：NJESD-30 代码：R-PDSO-G24
JESD-609代码：e3长度：7.8 mm
端子数量：24最高工作温度：70 °C
最低工作温度：最大输出时钟频率：700 MHz
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260主时钟/晶体标称频率：35 MHz
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压：3.465 V最小供电电压：3.135 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：4.4 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHERBase Number Matches：1

ICS844003AGTLF 数据手册

 浏览型号ICS844003AGTLF的Datasheet PDF文件第2页浏览型号ICS844003AGTLF的Datasheet PDF文件第3页浏览型号ICS844003AGTLF的Datasheet PDF文件第4页浏览型号ICS844003AGTLF的Datasheet PDF文件第5页浏览型号ICS844003AGTLF的Datasheet PDF文件第6页浏览型号ICS844003AGTLF的Datasheet PDF文件第7页 
PRELIMINARY  
FEMTOCLOCKS™ CRYSTAL-TO-LVDS  
FREQUENCY SYNTHESIZER  
ICS844003  
GENERAL DESCRIPTION  
FEATURES  
• Three LVDS outputs on two banks, A Bank with one LVDS  
pair and B Bank with 2 LVDS output pairs  
The ICS844003 is a 3 differential output LVDS  
ICS  
Synthesizer designed to generate Ethernet reference  
HiPerClockS™  
clock frequencies and is a member of the  
HiPerClocks™ family of high performance clock  
solutions from IDT. Using a 31.25MHz or  
• Using a 31.25MHz or 26.041666MHz crystal, the two output  
banks can be independently set for 625MHz, 312.5MHz,  
156.25MHz or 125MHz  
26.041666MHz, 18pF parallel resonant crystal, the following  
frequencies can be generated based on the settings of four  
frequency select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]):  
625MHz, 312.5MHz, 156.25MHz, and 125MHz. The ICS844003  
has two output banks, Bank A with one differential LVDS output  
pair and Bank B with two differential LVDS output pairs.  
• Selectable crystal oscillator interface or LVCMOS/LVTTL  
single-ended input  
• VCO range: 560MHz to 700MHz  
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):  
0.63ps (typical)  
• 3.3V output supply mode  
The two banks have their own dedicated frequency select  
pins and can be independently set for the frequencies  
mentioned above. The ICS844003 uses IDT’s 3rd generation  
low phase noise VCO technology and can achieve 1ps or  
lower typical rms phase jitter, easily meeting Ethernet jitter  
requirements. The ICS844003 is packaged in a small 24-  
pin TSSOP package.  
• 0°C to 70°C ambient operating temperature  
• Available in both standard (RoHS5) and lead-free (RoHS 6)  
packages  
PIN ASSIGNMENT  
1
DIV_SELB0  
VCO_SEL  
MR  
24  
23  
22  
DIV_SELB1  
VDDO_B  
QB0  
2
3
4
VDDO_A  
nQB0  
21  
20  
19  
18  
17  
16  
15  
14  
13  
5
6
7
QB1  
QA0  
nQA0  
OEB  
OEA  
FB_DIV  
nQB1  
XTAL_SEL  
TEST_CLK  
8
9
10  
11  
12  
XTAL_IN  
XTAL_OUT  
GND  
VDDA  
VDD  
BLOCK DIAGRAM  
DIV_SELA1  
DIV_SELA0  
Pullup  
OEA  
ICS844003  
24-Lead TSSOP  
4.40mm x 7.8mm x 0.92mm  
package body  
DIV_SELA[1:0]  
Pullup  
VCO_SEL  
QA0  
0 0 ÷1  
nQA0  
G Package  
Top View  
Pulldown  
0 1 ÷2 (default)  
1 0 ÷4  
TEST_CLK  
XTAL_IN  
0
1
0
1
1 1 ÷5  
Phase  
Detector  
VCO  
OSC  
XTAL_OUT  
XTAL_SEL  
Pullup  
QB0  
FB_DIV  
0 0 ÷1  
nQB0  
0 1 ÷2  
0 = ÷20 (default)  
1 = ÷24  
1 0 ÷4 (default)  
1 1 ÷5  
QB1  
Pulldown  
FB_DIV  
DIV_SELB[1:0]  
MR  
nQB1  
Pulldown  
Pullup  
OEB  
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization  
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.  
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER  
1
ICS844003AG REV A JANUARY 15, 2008  
1234567...16

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