FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
ICS841654I
GENERAL DESCRIPTION
FEATURES
The ICS841654I is an optimized PCIe and sRIO clock
• Four differential HCSL clock outputs: configurable for PCIe
(100MHz) and sRIO (100MHz or 125MHz) clock signals
One REF_OUT LVCMOS/LVTTL clock output
ICS
HiPerClockS™
generator and member of the HiPerClocks™family
of high-performance clock solutions from IDT. The
device uses a 25MHz parallel crystal to generate
100MHz and 125MHz clock signals, replacing
• Selectable crystal oscillator interface, 25MHz, 18pF parallel
resonant crystal or LVCMOS/LVTTL single-ended reference
clock input
solutions requiring multiple oscillator and fanout buffer solutions.
The device has excellent phase jitter (< 1ps rms) suitable to clock
components requiring precise and low-jitter PCIe or sRIO or both
clock signals. Designed for telecom, networking and industrial
applications, the ICS841654I can also drive the high-speed sRIO
and PCIe SerDes clock inputs of communication processors,
DSPs, switches and bridges.
• Supports the following output frequencies:
100MHz or 125MHz
• VCO: 500MHz
• PLL bypass and output enable
• RMS phase jitter at 100MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.44ps (typical)
• Full 3.3V power supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
XTAL_IN
VDD
REF_OUT
GND
1
2
3
4
IREF
28
27
26
25
QA0
1
0
OSC
FSEL0
FSEL1
QB0
nQA0
XTAL_OUT
REF_IN
FemtoClock
QA0
0
PLL
÷NA
Pulldown
Pulldown
VCO = 500MHz
QA1
nQA0
VDDOA
GND
QA1
nQA1
24
23
22
nQB0
VDDOB
GND
QB1
nQB1
5
6
7
8
1
nQA1
REF_SEL
IREF
21
20
19
18
17
16
15
9
M = ÷20
QB0
MR/nOE
VDD
XTAL_IN
XTAL_OUT
GND
10
11
12
13
nREF_OE
BYPASS
REF_IN
REF_SEL
nQB0
÷NB
QB1
Pulldown
Pulldown
Pulldown
BYPASS
14
VDDA
nQB1
FSEL[0:1]
ICS841654I
28-Lead TSSOP
6.1mm x 9.7mm x 0.925mm
package body
MR/nOE
REF_OUT
G Package
Top View
Pullup
nREF_OE
IDT™ / ICS™ HCSL CLOCK GENERATOR
1
ICS841654AGI REV. A APRIL 17, 2008