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ICS841S012I PDF预览

ICS841S012I

更新时间: 2024-11-02 11:14:35
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
23页 190K
描述
Crystal-to-0.7V Differential HCSL/LVCMOS Frequency Synthesizer

ICS841S012I 数据手册

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Crystal-to-0.7V Differential HCSL/  
LVCMOS Frequency Synthesizer  
ICS841S012I  
DATA SHEET  
NRND  
GENERAL DESCRIPTION  
FEATURES  
The ICS841S012I is an optimized PCIe, sRIO and  
Gigabit Ethernet Frequency Synthesizer and a  
member of HiperClocks™family of high perfor-  
mance clock solutions from IDT. The ICS841S012I  
uses a 25MHz parallel resonant crystal to gener-  
To 0.7V differential HCSL outputs (Bank A), configurable for  
PCIe (100MHz or 250MHz) and sRIO (100MHz or 125MHz)  
clock signals  
ICS  
HiPerClockS™  
Eight LVCMOS/LVTTL outputs (Banks B/C),  
18Ω typical output impedance  
ate 33.33MHz - 200MHz clock signals, replacing multiple  
oscillator and fanout buffer solutions. The device supports  
0.25ꢀ center-spread, and -0.5ꢀ doꢁn- spread clocking ꢁith  
tꢁo spread select pins (SSC[1:0]). The VCO operates at a fre-  
quency of 2GHz. The device has three output banks: Bank A  
ꢁith tꢁo HCSL outputs, 100MHz – 250MHz; Bank B ꢁith seven  
33.33MHz – 200MHz LVCMOS/ LVTTL outputs; and Bank C  
ꢁith one 33.33MHz – 200MHz LVCMOS/LVTTL output.  
To REF_OUT LVCMOS/LVTTL clock outputs,  
23Ω typical output impedance  
• Selectable crystal oscillator interface, 25MHz, 18pF parallel  
resonant crystal or one LVCMOS/LVTTL single-ended  
reference clock input  
• Supports the folloꢁing output frequencies:  
HCSL Bank A: 100MHz, 125MHz, 200MHz and 250MHz  
LVCMOS/LVTTL Bank B/C: 33.33MHz, 50MHz, 66.67MHz,  
100MHz, 125MHz, 133.33MHz, 166.67MHz and 200MHz  
All Banks A, B and C have their oꢁn dedicated frequency  
select pins and can be independently set for the frequencies  
mentioned above. The loꢁ jitter characteristic of the  
ICS841S012I makes it an ideal clock source for PCIe, sRIO  
and Gigabit Ethernet applications. Designed for netꢁorking and  
industrial applications, the ICS841S012I can also drive the high-  
speed clock inputs of communication processors, DSPs,  
sꢁitches and bridges.  
• VCO: 2GHz  
• Spread spectrum clock: 0.25ꢀ center-spread (typical) and  
-0.6ꢀ doꢁn-spread (typical)  
• PLL bypass and output enable  
• RMS period jitter: 20ps (typical), QB outputs  
• Full 3.3V supply mode  
• -40°C to 85°C ambient operating temperature  
• Available in lead-free (RoHS 6) package  
• Not Recommended for Neꢁ Designs  
PIN ASSIGNMENT  
56 55 54 53 52 51 50 49 48 47 46 45 44 43  
42  
41  
VDD  
REF_OUT0  
REF_OUT1  
GND  
1
VDDOC  
QC  
2
GND  
QBC_OE  
VDDA  
VDDA  
GND  
GND  
IREF  
QA0  
3
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
4
5
ICS841S012I  
GND  
56-Lead VFQFN  
6
REF_IN  
VDD  
8mm x 8mm x 0.925mm  
package body  
7
REF_SEL  
XTAL_IN  
XTAL_OUT  
BYPASS  
8
9
K Package  
Top Vieꢁ  
10  
11  
12  
13  
14  
nQA0  
QA1  
nQA1  
REF_OE  
nMR  
VDD  
VDD  
15 16 17 18 19 20 21 22 23 24 25 26 27 28  
ICS841S012BKI REVISION A NOVEMBER 10, 2009  
1
©2009 Integrated Device Technology, Inc.  

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