®
ICS841N254I
FEMTOCLOCK NG
Crystal-to-LVDS/HCSL Clock Synthesizer
DATA SHEET
General Description
Features
The ICS841N254I is a 4-output clock synthesizer designed for S-RIO
1.3 and 2.0 reference clock applications. The device generates four
copies of a selectable 250MHz, 156.25MHz, 125MHz or 100MHz
clock signal with excellent phase jitter performance. The four outputs
are organized in two banks of two LVDS and two HCSL ouputs.The
device uses IDT’s fourth generation FemtoClock® NG technology for
an optimum of high clock frequency and low phase noise
performance, combined with a low power consumption and high
power supply noise rejection. The synthesized clock frequency and
the phase-noise performance are optimized for driving RIO 1.3 and
2.0 SerDes reference clocks. The device supports 3.3V and 2.5V
voltage supplies and is packaged in a small 32-lead VFQFN
package. The extended temperature range supports wireless
infrastructure, telecommunication and networking end equipment
requirements.
• Fourth generation FemtoClock® (NG) technology
• Selectable 250MHz, 156.25MHz, 125MHz or 100MHz output
clock synthesized from a 25MHz fundamental mode crystal
• Four differential clock outputs (two LVDS and two HCSL outputs)
• Crystal interface designed for 25MHz,
parallel resonant crystal
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1MHz - 20MHz): 0.27ps (typical)
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(12kHz - 20MHz): 0.32ps (typical)
• Power supply noise rejection PSNR: -50dB (typical)
• LVCMOS interface levels for the frequency select input
• Full 3.3V or 2.5V supply voltage
• Available in both standard (RoHS 5) and Lead-free (RoHS 6)
packages
• -40°C to 85°C ambient operating temperature
Function Table
Inputs
Pin Assignment
Output Frequency with
F_SEL1
F_SEL0
fXTAL = 25MHz
156.25MHz
125MHz
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
VDD
IREF
24
23
22
21
20
0 (default)
0 (default)
nc
VDDA
GND
nQA0
QA0
0
1
1
1
0
1
ICS841N254I
32-lead VFQFN
K Package
100MHz
nc
250MHz
5mm x 5mm x 0.925mm
package body
VDDOA
GND
REF_CLK
nOEA
VDD
nQA1
QA1
19
18
17
NOTE: F_SEL[1:0] are asynchronous controls.
Top View
GND
9
10 11 12 13 14 15 16
Block Diagram
QA0
nQA0
XTAL_IN
LVDS
LVDS
HCSL
HCSL
1
0
OSC
0
1
÷N
XTAL_OUT
REF_CLK
PFD
&
LPF
FemtoClock® NG
VCO
QA1
nQA1
Pulldown
625MHz
QB0
nQB0
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
÷25
REF_SEL
BYPASS
F_SEL[0:1]
nOEA
2
QB1
nQB1
nOEB
IREF
ICS841N254AKI REVISION A APRIL 18, 2011
1
©2011 Integrated Device Technology, Inc.