Datasheet > ICS8344AY-01T

ICS8344AY-01T

更新时间： 2024-10-01 22:15:43

品牌	Logo	应用领域
矽成 - ICSI		/
页数	文件大小	规格书
16页	142K
描述
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER

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ICS8344AY-01T 数据手册

ICS8344-01

LOW SKEW, 1-TO-24

DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER

Integrated

Circuit

Systems, Incꢀ

GENERAL DESCRIPTION

FEATURES

The ICS8344-01 is a low voltage, low skew • 24 LVCMOS outputs, 7Ω typical output impedance

fanout buffer and a member of the HiPerClockS™

family of High Performance Clock Solutions from

• 2 selectable CLKx, nCLKx inputs

HiPerClockS™

ICS. The ICS8344-01 has two selectable clock

inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs

• CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the

following input levels: LVDS, LVPECL, LVHSTL, SSTL,

HCSL

can accept most standard differential input levels. The

ICS8344-01 is designed to translate any differential signal

levels to LVCMOS levels. The low impedance LVCMOS out-

puts are designed to drive 50Ω series or parallel terminated

transmission lines. The effective fanout can be increased to

48 by utilizing the ability of the outputs to drive two series

terminated lines. Redundant clock applications can make use

of the dual clock input. The dual clock inputs also facilitate

board level testing. The clock enable is internally synchro-

nized to eliminate runt pulses on the outputs during asyn-

chronous assertion/deassertion of the clock enable pin. The

outputs are driven low when disabled. The ICS8344-01 is

characterized at full 3.3V, full 2.5V and mixed 3.3V input and

2.5V output operating supply modes.

• Output frequency up to 250MHz

• Translates any single ended input signal to LVCMOS with

resistor bias on nCLK input

• Synchronous clock enable

• Output skew: 200 ps (maximum)

• Part-to-part skew: 900ps (maximum)

• Bank skew: 85ps (maximum)

• Propagation delay: 5ns (maximum)

• 3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes

• 0°C to 70°C ambient operating temperature

• Industrial temperature information available upon request

Guaranteed output and part-to-part skew characteristics

make the ICS8344-01 ideal for those clock distribution

applications demanding well defined performance and

repeatability.

BLOCK DIAGRAM

PIN ASSIGNMENT

CLK_SEL

CLK0

nCLK0

48 47 46 45 44 43 42 41 40 39 38 37

Q16

Q17

V^DDO

GND

Q18

Q19

Q20

Q21

V^DDO

GND

Q22

Q23

CLK1

nCLK1

V^DDO

GND

Q0 - Q7

Q8 - Q15

Q16 - Q23

ICS8344-01

V^DDO

GND

13 14 15 16 17 18 19 20 21 22 23 24

CLK_EN

48-Lead LQFP

7mm x 7mm x 1.4mm

Y Package

Top View

8344AY-01

www.icst.com/products/hiperclocks.html

REV. B AUGUST 6, 2001

12 3 4 5 6 7...16

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与ICS8344AY-01T相关器件

型号	品牌	获取价格	描述	数据表
ICS8344AYI-01	IDT	获取价格	LOW SKEW, 1-TO-24 DIFFERENTIAL -TO-LVCMOS/LVTTL FANOUT BUFFER
ICS8344AYI-01LF	IDT	获取价格	LOW SKEW, 1-TO-24 DIFFERENTIAL -TO-LVCMOS/LVTTL FANOUT BUFFER
ICS8344AYI-01LFT	IDT	获取价格	LOW SKEW, 1-TO-24 DIFFERENTIAL -TO-LVCMOS/LVTTL FANOUT BUFFER
ICS8344AYI-01T	IDT	获取价格	LOW SKEW, 1-TO-24 DIFFERENTIAL -TO-LVCMOS/LVTTL FANOUT BUFFER
ICS8344BY	ICSI	获取价格	LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
ICS8344BY-01	IDT	获取价格	Low Skew Clock Driver, 24 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM
ICS8344BY-01LF	IDT	获取价格	Low Skew Clock Driver, 24 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM
ICS8344BY-01T	ETC	获取价格	Buffer/Driver
ICS8344BYI	ICSI	获取价格	LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
ICS8344BYILF	IDT	获取价格	Low Skew Clock Driver, 8344 Series, 24 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7

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