Datasheet > ICS8344I-01

ICS8344I-01

更新时间： 2024-10-02 03:00:51

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
13页	241K
描述
LOW SKEW, 1-TO-24 DIFFERENTIAL -TO-LVCMOS/LVTTL FANOUT BUFFER

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

ICS8344I-01 数据手册

PRELIMINARY

LOW SKEW, 1-TO-24 DIFFERENTIAL-

TO-LVCMOS/LVTTL FANOUT BUFFER

ICS8344I-01

GENERAL DESCRIPTION

FEATURES

The ICS8344I-01 is a low voltage, low skew

• Twenty-four LVCMOS/LVTTL outputs,

7Ω typical output impedance

ICS

HiPerClockS™

fanout buffer and a member of the HiPerClockS™

family of High Performance Clock Solutions from

• Two selectable differential CLKx, nCLKx inputs

IDT. The ICS8344I-01 has two selectable clock in-

puts. The CLKx, nCLKx pairs can accept most

• CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the

following input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL

standard differential input levels. The ICS8344I-01 is designed

to translate any differential signal level to LVCMOS/LVTTL lev-

els. The low impedance LVCMOS/LVTTL outputs are designed

to drive 50Ω series or parallel terminated transmission lines.

The effective fanout can be increased to 48 by utilizing the

ability of the outputs to drive two series terminated lines.

Redundant clock applications can make use of the dual clock

inputs which also facilitate board level testing. The clock

enable is internally synchronized to eliminate runt pulses on

the outputs during asynchronous assertion/deassertion of the

clock enable pin. The outputs are driven low when disabled.

The ICS8344I-01 is characterized at full 3.3V, full 2.5V and

mixed 3.3V input and 2.5V output operating supply modes.

• Maximum output frequency: 200MHz

• Translates any single ended input signal to LVCMOS/LVTTL

with resistor bias on nCLK input

• Synchronous clock enable

• Output skew: 250ps (maximum)

• Part-to-part skew: 1ns (maximum)

• Bank skew: 125ps (maximum)

• Propagation delay: 5.25ns (maximum)

• Output supply modes:

Core/Output

3.3V/3.3V

Guaranteed output and part-to-part skew characteristics make

the ICS8344I-01 ideal for those clock distribution applications

demanding well defined performance and repeatability.

2.5V/2.5V

3.3V/2.5V

• -40°C to 85°C ambient operating temperature

• Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

BLOCK DIAGRAM

PIN ASSIGNMENT

CLK_SEL

CLK0

48 47 46 45 44 43 42 41 40 39 38 37

nCLK0

Q16

Q17

V^DDO

GND

Q18

Q19

Q20

Q21

V^DDO

GND

Q22

Q23

CLK1

nCLK1

V^DDO

GND

Q0:Q7

ICS8344-01

48-Lead LQFP

7mm x 7mm x 1.4mm

package body

Y Package

Q8:Q15

Q16:Q23

V^DDO

GND

Top View

13 14 15 16 17 18 19 20 21 22 23 24

CLK_EN

The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization

and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.

IDT^™/ ICS^™LVCMOS/LVTTL FANOUT BUFFER

ICS8344AYI-01 REV. B MAY 10, 2007

12 3 4 5 6 7...13

中文翻译

下载PDF

与ICS8344I-01相关器件

型号	品牌	获取价格	描述	数据表
ICS83840	ICSI	获取价格	DDR SDRAM MUX
ICS83840AH	ICSI	获取价格	DDR SDRAM MUX
ICS83840AHLF	ICSI	获取价格	DDR SDRAM MUX
ICS83840AHLFT	ICSI	获取价格	DDR SDRAM MUX
ICS83840AHT	ICSI	获取价格	DDR SDRAM MUX
ICS83840B	ICSI	获取价格	DDR SDRAM MUX
ICS83840BH	ICSI	获取价格	DDR SDRAM MUX
ICS83840BHLF	ICSI	获取价格	DDR SDRAM MUX
ICS83840BHLFT	ICSI	获取价格	DDR SDRAM MUX
ICS83840BHT	ICSI	获取价格	DDR SDRAM MUX

与ICS8344I-01相关文章

塔塔电子与力积电达成技术转让协议，携手建设印度首座晶圆厂
2024-09-29

38
英特尔震撼发布：128核心256线程的至强6性能核处理器
2024-09-29

32
SK海力士量产12层HBM3E，容量高达36GB
2024-09-27

28
意法半导体传感器驱动Sphere，开启沉浸式电影新时代
2024-09-27

40

产品中心

服务支持

精选活动

关于我们

帮助中心

ICS8344I-01

ICS8344I-01 数据手册

与ICS8344I-01相关器件

与ICS8344I-01相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

ICS8344I-01

ICS8344I-01 数据手册

与ICS8344I-01相关器件

与ICS8344I-01相关文章

您还可以找

您在本页遇到什么问题？