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ICS8344BY-01LF PDF预览

ICS8344BY-01LF

更新时间: 2024-10-02 14:33:55
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
13页 120K
描述
Low Skew Clock Driver, 24 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-026, LQFP-48

ICS8344BY-01LF 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:QFP
包装说明:7 X 7 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-026, LQFP-48针数:48
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.21Is Samacsys:N
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQFP-G48
JESD-609代码:e3长度:7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:48实输出次数:24
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260传播延迟(tpd):5 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.2 ns
座面最大高度:1.6 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:7 mm
最小 fmax:250 MHzBase Number Matches:1

ICS8344BY-01LF 数据手册

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ICS8344-01  
LOW SKEW, 1-TO-24  
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER  
Integrated  
Circuit  
Systems, Incꢀ  
GENERAL DESCRIPTION  
FEATURES  
The ICS8344-01 is a low voltage, low skew  
24 LVCMOS outputs, 7typical output impedance  
,&6  
fanout buffer and a member of the HiPerClockS™  
family of High Performance Clock Solutions from  
ICS. The ICS8344-01 is designed to translate any  
differential signal levels to LVCMOS levels. The  
Output frequency up to 250MHz  
HiPerClockS™  
85ps bank skew, 200ps output skew, 900ps part to part  
skew  
low impedance LVCMOS outputs are designed to drive 50Ω  
series or parallel terminated transmission lines. The effective  
fanout can be increased to 48 by utilizing the ability of the  
outputs to drive two series terminated lines. Redundant clock  
applications can make use of the dual clock input. The dual  
clock inputs also facilitate board level testing. The output  
enable is synchronous which eliminates the runt clock pulses  
which occur during asynchronous enabling and disabling of  
the outputs. The outputs are driven low when disabled. The  
ICS8344-01 is characterized at full 3.3V, full 2.5V and mixed  
3.3V input and 2.5V output operating supply modes.  
Translates any differential input signal (PECL, HSTL, LVDS)  
to LVCMOS without external bias networks  
Translates any single ended input signal to LVCMOS with  
resistor bias on nCLK input  
Translates any single ended input signal to inverted  
LVCMOS with resistor bias on CLK input  
LVCMOS control inputs  
Synchronous clock enable  
3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes  
Guaranteed output and part-to-part skew characteristics  
make the ICS8344-01 ideal for those clock distribution  
applications demanding well defined performance and  
repeatability.  
48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm  
package body, 0.5mm package lead pitch  
0°C to 70°C ambient operating temperature  
Industrial temperature version available upon request  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
CLK_SEL  
CLK0  
48 47 46 45 44 43 42 41 40 39 38 37  
Q16  
Q17  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
Q7  
2
Q6  
0
nCLK0  
VDDO  
GND  
Q18  
3
VDDO  
GND  
Q5  
CLK1  
1
nCLK1  
4
5
Q19  
6
Q0 - Q7  
Q4  
ICS8344-01  
Q20  
7
Q3  
Q21  
8
Q2  
O8 - Q15  
VDDO  
GND  
Q22  
9
VDDO  
GND  
Q1  
10  
11  
12  
O16 - Q23  
Q23  
Q0  
13 14 15 16 17 18 19 20 21 22 23 24  
LE  
Q
nD  
CLK_EN  
OE  
48-Lead LQFP  
Y Package  
Top View  
8344-01  
www.icst.com  
REV. A JANUARY 30, 2001  
1

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