Datasheet > ICS8344BYI-T

ICS8344BYI-T

更新时间： 2024-10-01 22:15:47

品牌	Logo	应用领域
矽成 - ICSI		逻辑集成电路驱动
页数	文件大小	规格书
16页	144K
描述
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER

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ICS8344BYI-T 数据手册

ICS8344I

LOW SKEW, 1-TO-24

DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER

Integrated

Circuit

Systems, Incꢀ

GENERAL DESCRIPTION

FEATURES

The ICS8344I is a low voltage, low skew fanout • 24 LVCMOS outputs, 7Ω typical output impedance

buffer and a member of the HiPerClockS™

• 2 selectable differential clock input pairs for redundant clock

family of High Performance Clock Solutions from

applications

HiPerClockS™

ICS. The ICS8344I has two selectable clock in-

puts. The CLK0, nCLK0 and CLK1, nCLK1 pairs

• CLKx, nCLKx pair can accept the following differential input

can accept most standard differential input levels. The

ICS8344I is designed to translate any differential signal lev-

els to LVCMOS levels. The low impedance LVCMOS outputs

are designed to drive 50Ω series or parallel terminated trans-

mission lines. The effective fanout can be increased to 48 by

utilizing the ability of the outputs to drive two series termi-

nated lines. Redundant clock applications can make use of

the dual clock input. The dual clock inputs also facilitate board

level testing. ICS8344I is characterized at full 3.3V, full 2.5V

and mixed 3.3V input and 2.5V output operating supply modes.

levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL

• Maximum output frequency up to 100MHz

• Translates any single-ended input signal to LVCMOS with

resistor bias on nCLK input

• Multiple output enable pins for disabling unused outputs in

reduced fanout applications

• Output skew: 275ps (maximum)

• Part-to-part skew: 600ps (maximum)

• Bank skew: 150ps (maximum)

Guaranteed output and part-to-part skew characteristics

make the ICS8344I ideal for those clock distribution applica-

tions demanding well defined performance and repeatability.

• 3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes

• -40°C to 85°C ambient operating temperature

BLOCK DIAGRAM

PIN ASSIGNMENT

CLK_SEL

48 47 46 45 44 43 42 41 40 39 38 37

Q16

Q17

VDDO

GND

Q18

Q19

Q20

Q21

V^DDO

GND

Q22

Q23

CLK0

nCLK0

V^DDO

GND

CLK1

nCLK1

Q0 - Q7

OE1

ICS8344I

Q8 - Q15

V^DDO

GND

OE2

Q16 - Q23

13 14 15 16 17 18 19 20 21 22 23 24

OE3

48-Lead LQFP

7mm x 7mm x 1.4mm package body

Y Package

Top View

8344BYI

www.icst.com/products/hiperclocks.html

REV. A AUGUST 9, 2001

12 3 4 5 6 7...16

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与ICS8344BYI-T相关器件

型号	品牌	获取价格	描述	数据表
ICS8344BYLF	IDT	获取价格	Low Skew Clock Driver, 24 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM
ICS8344BYT	ICSI	获取价格	LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
ICS8344I	ICSI	获取价格	LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
ICS8344I-01	IDT	获取价格	LOW SKEW, 1-TO-24 DIFFERENTIAL -TO-LVCMOS/LVTTL FANOUT BUFFER
ICS83840	ICSI	获取价格	DDR SDRAM MUX
ICS83840AH	ICSI	获取价格	DDR SDRAM MUX
ICS83840AHLF	ICSI	获取价格	DDR SDRAM MUX
ICS83840AHLFT	ICSI	获取价格	DDR SDRAM MUX
ICS83840AHT	ICSI	获取价格	DDR SDRAM MUX
ICS83840B	ICSI	获取价格	DDR SDRAM MUX

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