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ICS8344AYI-01 PDF预览

ICS8344AYI-01

更新时间: 2024-10-02 03:20:03
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
13页 241K
描述
LOW SKEW, 1-TO-24 DIFFERENTIAL -TO-LVCMOS/LVTTL FANOUT BUFFER

ICS8344AYI-01 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP, QFP48,.35SQ,20针数:48
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.76其他特性:ALSO OPERATES WITH 3.3V SUPPLY
系列:8344输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G48JESD-609代码:e0
长度:7 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
最大I(ol):0.027 A湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:48实输出次数:24
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP48,.35SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):240电源:2.5/3.3 V
Prop。Delay @ Nom-Sup:5.25 ns传播延迟(tpd):5.25 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.25 ns
座面最大高度:1.6 mm子类别:Clock Drivers
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:7 mm
Base Number Matches:1

ICS8344AYI-01 数据手册

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PRELIMINARY  
LOW SKEW, 1-TO-24 DIFFERENTIAL-  
TO-LVCMOS/LVTTL FANOUT BUFFER  
ICS8344I-01  
GENERAL DESCRIPTION  
FEATURES  
The ICS8344I-01 is a low voltage, low skew  
Twenty-four LVCMOS/LVTTL outputs,  
7Ω typical output impedance  
ICS  
HiPerClockS™  
fanout buffer and a member of the HiPerClockS™  
family of High Performance Clock Solutions from  
Two selectable differential CLKx, nCLKx inputs  
IDT. The ICS8344I-01 has two selectable clock in-  
puts. The CLKx, nCLKx pairs can accept most  
CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the  
following input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL  
standard differential input levels. The ICS8344I-01 is designed  
to translate any differential signal level to LVCMOS/LVTTL lev-  
els. The low impedance LVCMOS/LVTTL outputs are designed  
to drive 50Ω series or parallel terminated transmission lines.  
The effective fanout can be increased to 48 by utilizing the  
ability of the outputs to drive two series terminated lines.  
Redundant clock applications can make use of the dual clock  
inputs which also facilitate board level testing. The clock  
enable is internally synchronized to eliminate runt pulses on  
the outputs during asynchronous assertion/deassertion of the  
clock enable pin. The outputs are driven low when disabled.  
The ICS8344I-01 is characterized at full 3.3V, full 2.5V and  
mixed 3.3V input and 2.5V output operating supply modes.  
Maximum output frequency: 200MHz  
Translates any single ended input signal to LVCMOS/LVTTL  
with resistor bias on nCLK input  
Synchronous clock enable  
Output skew: 250ps (maximum)  
Part-to-part skew: 1ns (maximum)  
Bank skew: 125ps (maximum)  
Propagation delay: 5.25ns (maximum)  
Output supply modes:  
Core/Output  
3.3V/3.3V  
Guaranteed output and part-to-part skew characteristics make  
the ICS8344I-01 ideal for those clock distribution applications  
demanding well defined performance and repeatability.  
2.5V/2.5V  
3.3V/2.5V  
-40°C to 85°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
CLK_SEL  
CLK0  
48 47 46 45 44 43 42 41 40 39 38 37  
0
nCLK0  
Q16  
Q17  
VDDO  
GND  
Q18  
Q19  
Q20  
Q21  
VDDO  
GND  
Q22  
Q23  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
Q7  
2
Q6  
CLK1  
nCLK1  
1
3
VDDO  
GND  
Q5  
Q0:Q7  
4
ICS8344-01  
5
48-Lead LQFP  
7mm x 7mm x 1.4mm  
package body  
Y Package  
6
Q4  
Q8:Q15  
Q16:Q23  
7
Q3  
8
Q2  
9
VDDO  
GND  
Q1  
Top View  
10  
11  
12  
Q0  
LE  
nD  
13 14 15 16 17 18 19 20 21 22 23 24  
Q
CLK_EN  
OE  
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization  
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.  
IDT/ ICSLVCMOS/LVTTL FANOUT BUFFER  
1
ICS8344AYI-01 REV. B MAY 10, 2007  

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ICS8344BYILF IDT

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