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ICS8305AGLF PDF预览

ICS8305AGLF

更新时间: 2024-11-03 13:08:35
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
17页 2141K
描述
Low Skew Clock Driver, 8305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, 4.40 X 3 MM, 0.92 MM HEIGHT, MO-153, TSSOP-16

ICS8305AGLF 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.16Is Samacsys:N
系列:8305输入调节:DIFFERENTIAL MUX
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:5 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:16
实输出次数:4最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:4 ns
传播延迟(tpd):4 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.035 ns座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
最小 fmax:350 MHzBase Number Matches:1

ICS8305AGLF 数据手册

 浏览型号ICS8305AGLF的Datasheet PDF文件第2页浏览型号ICS8305AGLF的Datasheet PDF文件第3页浏览型号ICS8305AGLF的Datasheet PDF文件第4页浏览型号ICS8305AGLF的Datasheet PDF文件第5页浏览型号ICS8305AGLF的Datasheet PDF文件第6页浏览型号ICS8305AGLF的Datasheet PDF文件第7页 
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/  
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER  
ICS8305  
General Description  
Features  
The ICS8305 is a low skew, 1-to-4, Differential/  
Four LVCMOS / LVTTL outputs, 7output impedance  
S
IC  
LVCMOS-to-LVCMOS/LVTTL Fanout Buffer and a  
member of the HiPerClockSfamily of High  
Performance Clock Solutions from IDT. The  
ICS8305 has selectable clock inputs that accept  
Selectable differential or LVCMOS / LVTTL clock inputs  
HiPerClockS™  
CLK, nCLK pair can accept the following differential input levels:  
LVPECL, LVDS, LVHSTL, HCSL, SSTL  
LVCMOS_CLK supports the following input types: LVCMOS,  
either differential or single ended input levels. The clock enable is  
internally synchronized to eliminate runt pulses on the outputs  
during asynchronous assertion/deassertion of the clock enable  
pin. Outputs are forced LOW when the clock is disabled. A  
separate output enable pin controls whether the outputs are in the  
active or high impedance state.  
LVTTL  
Maximum output frequency: 350MHz  
Output skew: 35ps (maximum)  
Part-to-part skew: 700ps (maximum)  
Additive phase jitter, RMS: 0.04ps (typical)  
Guaranteed output and part-to-part skew characteristics make the  
ICS8305 ideal for those applications demanding well defined  
performance and repeatability.  
Power supply modes:  
Core/Output  
3.3V/3.3V  
3.3V/2.5V  
3.3V/1.8V  
3.3V/1.5V  
0°C to 70°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
Pin Assignment  
Block Diagram  
GND  
OE  
VDD  
1
2
16 Q0  
Pullup  
CLK_EN  
D
15  
VDDO  
Q1  
GND  
Q2  
Q
14  
13  
3
4
LE  
CLK_EN  
CLK  
nCLK  
Pulldown  
LVCMOS_CLK  
0
12  
11  
10  
9
5
6
7
8
Q0  
Pulldown  
Pullup/  
Pulldown  
VDDO  
Q3  
CLK  
nCLK  
1
CLK_SEL  
LVCMOS_CLK  
GND  
Q1  
Q2  
Q3  
Pullup  
Pullup  
CLK_SEL  
ICS8305  
16-Lead TSSOP  
4.4mm x 3.0mm x 0.925mm  
package body  
G Package  
OE  
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER  
1
ICS8305AG REV. C OCTOBER 23, 2008  

ICS8305AGLF 替代型号

型号 品牌 替代类型 描述 数据表
8305AGLFT IDT

完全替代

LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL LVCMOS-TO-LVCMOS/LVTTL
8305AGLF IDT

完全替代

LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL LVCMOS-TO-LVCMOS/LVTTL

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