ICS8308I
LOW SKEW, 1-TO-8
DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS8308I is a low-skew, 1-to-8 Fanout Buffer
• 8 LVCMOS/LVTTL outputs (7Ω typical output impedance)
and a member of the HiPerClockS™ family of
High Performance Clock Solutions from ICS.The
ICS8308I has two selectable clock inputs. The
• Selectable LVCMOS_CLK or differential CLK, nCLK
inputs
CLK, nCLK pair can accept most differential input
• CLK, nCLK pair can accept the following differential
levels. The LVCMOS_CLK can accept LVCMOS or LVTTL
input levels. The low impedance LVCMOS/LVTTL outputs
are designed to drive 50Ω series or parallel terminated
transmission lines. The effective fanout can be increased
from 8 to 16 by utilizing the ability of the outputs to drive two
series terminated transmission lines.
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum Output Frequency: 350MHz
• Output Skew: (3.3V 5ꢀ): 100ps (maximum)
• Part to Part Skew: (3.3V 5ꢀ): 1ns (maximum)
• SupplyVoltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
The ICS8308I is characterized for 3.3V core/3.3V output,
3.3V core/2.5V output or 2.5V core/2.5V output operation.
Guaranteed output and part-part skew characteristics make
the 8308I ideal for those clock distribution applications requiring
well defined performance and repeatability.
• -40°C to 85°C ambient operating temperature
• Available in both, Standard and RoHS/Lead-Free
compliant packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Pullup
1
24
23
22
21
20
19
18
17
16
15
14
13
CLK_EN
D
Q0
GND
CLK_SEL
LVCMOS_CLK
CLK
VDDO
Q2
GND
Q3
VDDO
Q4
2
3
4
5
Q
LE
Pullup
LVCMOS_CLK
1
Q0
Pullup
CLK
nCLK
CLK_EN
OE
6
7
8
9
10
11
12
0
Pulldown
nCLK
GND
Q5
VDDO
Q6
GND
Q7
Q1
Q2
Q3
VDD
GND
Q1
VDDO
Pullup
CLK_SEL
Q4
Q5
ICS8308I
24-Lead, 300-MIL TSSOP
4.4mm x 7.8mm x 0.92mm body package
G Package
Q6
Q7
TopView
Pullup
OE
8308AGI
www.icst.com/products/hiperclocks.html
REV.B JULY 25, 2005
1