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ICS8312AY PDF预览

ICS8312AY

更新时间: 2024-11-02 22:55:23
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
12页 253K
描述
LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER

ICS8312AY 数据手册

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ICS8312  
Integrated  
Circuit  
Systems, Inc.  
LOW  
S
KEW, 1-TO-12  
LVCMOS / LVTTL FANOUT  
BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS8312 is a low skew, 1-to-12 LVCMOS /  
12 LVCMOS / LVTTL outputs  
LVCMOS / LVTTL clock input  
Maximum output frequency: 250MHz  
Output skew: 150ps (maximum)  
ICS  
LVTTL Fanout Buffer and a member of the  
HiPerClockS™family of High Performance Clock  
Solutions from ICS. The ICS8312 single ended  
clock input accepts LVCMOS or LVTTL input lev-  
HiPerClockS™  
els. The low impedance LVCMOS outputs are designed to  
drive 50series or parallel terminated transmission lines.The  
effective fanout can be increased from 12 to 24 by utilizing  
the ability of the outputs to drive two series terminated lines.  
Operating supply modes:  
Core/Output  
3.3V/3.3V,  
2.5V/2.5V,  
1.8V/1.8V,  
3.3V/2.5V,  
3.3V/1.8V,  
The ICS8312 is characterized at full 3.3V, 2.5V, and 1.8V,  
mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating  
supply modes. Guaranteed output and part-to-part skew char-  
acteristics along with the 1.8V output capabilities makes the  
ICS8312 ideal for high performance, single ended applica-  
tions that also require a limited output voltage.  
2.5V/1.8V  
0°C to 85°C ambient operating temperature  
Lead-Free package available  
Industrial temperature information available upon request  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
32 31 30 29 28 27 26 25  
nD  
LE  
CLK_EN  
CLK  
Q
GND  
VDD  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
Q4  
VDDO  
Q5  
12  
CLK_EN  
CLK  
Q0:Q11  
GND  
Q6  
ICS8312  
GND  
OE  
VDDO  
Q7  
VDD  
GND  
GND  
9
10 11 12 13 14 15 16  
OE  
32-Lead LQFP  
7mm x 7mm x 1.4mm body package  
Y Pacakge  
TopView  
8312AY  
http://www.icst.com/products/hiperclocks.html  
REV. C JUNE 14, 2004  
1

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