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ICS542M PDF预览

ICS542M

更新时间: 2024-09-16 19:18:55
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
6页 136K
描述
Low Skew Clock Driver, 542 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH, SOIC-8

ICS542M 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:0.150 INCH, SOIC-8针数:8
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.16系列:542
输入调节:STANDARDJESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.9 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大频率@ Nom-Sup:156000000 Hz
功能数量:1反相输出次数:
端子数量:8实输出次数:2
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3/5 V
传播延迟(tpd):15 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.5 ns座面最大高度:1.75 mm
子类别:Prescaler/Multivibrators最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mm最小 fmax:156 MHz
Base Number Matches:1

ICS542M 数据手册

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DATASHEET  
CLOCK DIVIDER  
ICS542  
Description  
Features  
The ICS542 is cost effective way to produce a high-quality  
clock output divided from a clock input. The chip accepts a  
clock input up to 156 MHz at 3.3 V and produces a divide by  
2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs  
on the chip, one being a low-skew divide by two of the other.  
8-pin SOIC package  
Available in RoHS compliant package  
IDT’s lowest cost clock divider  
Low skew (500 ps) outputs. One is /2 of the other  
Easy to use with other generators and buffers  
Input clock frequency up to 156 MHz  
Output clock duty cycle of 45/55  
Power-down turns off chip  
For instance, if an 100 MHz input clock is used, the ICS542  
can produce low-skew 50 MHz and 25 MHz clocks, or low  
skew 25 MHz and 12.5 MHz clocks. The chip has an  
all-chip power-down mode that stops the outputs low, and  
an OE pin that tri-states the outputs.  
Output Enable  
See the ICS541 and ICS543 for other clock dividers, and  
the ICS501, 502, 511, 512, and 525 for clock multipliers.  
Advanced, low-power CMOS process  
Operating voltage of 3.3 V or 5 V  
Does not degrade phase noise - no PLL  
Available in industrial and commercial temperature  
ranges  
NOTE: EOL for non-green parts to occur on 5/13/10  
per PDN U-09-01  
Block Diagram  
VDD  
CLK1  
S1, S0  
Divider  
and  
/2  
Selection  
Circuitry  
CLK2  
Input Clock  
OE (both outputs)  
GND  
IDT™ / ICS™ CLOCK DIVIDER  
1
ICS542  
REV H 092209  

ICS542M 替代型号

型号 品牌 替代类型 描述 数据表
542MLFT IDT

完全替代

CLOCK DIVIDER
542MLF IDT

完全替代

CLOCK DIVIDER
542MILF IDT

完全替代

CLOCK DIVIDER

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ICS542MI IDT

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ICS542MILF IDT

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ICS542MILFT IDT

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Low Skew Clock Driver, 542 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.
ICS542MIT IDT

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Low Skew Clock Driver, 542 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.
ICS542MLF IDT

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Low Skew Clock Driver, 542 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.
ICS542MLFT IDT

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CLOCK DIVIDER
ICS542MT ICSI

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ICS542MT IDT

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Low Skew Clock Driver, 542 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.
ICS543 ICSI

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PRELIMINARY INFORMATION Clock Divider and 2X Multiplier
ICS543M ICSI

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PRELIMINARY INFORMATION Clock Divider and 2X Multiplier