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ICS5342VLF

更新时间： 2024-11-09 13:08:35

品牌	Logo	应用领域
艾迪悌 - IDT		时钟
页数	文件大小	规格书
35页	1294K
描述
Palette DAC, MOS, PQCC68, PLASTIC, LCC-68

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技术参数
数据手册

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ICS5342VLF 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	LCC
包装说明：	PLASTIC, LCC-68	针数：	68
Reach Compliance Code：	compliant	风险等级：	5.06
Is Samacsys：	N	地址总线宽度：	3
外部数据总线宽度：	8	JESD-30 代码：	S-PQCC-J68
JESD-609代码：	e3	长度：	24.23 mm
端子数量：	68	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	座面最大高度：	4.57 mm
标称供电电压：	5 V	表面贴装：	YES
技术：	MOS	端子面层：	MATTE TIN
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	24.23 mm	uPs/uCs/外围集成电路类型：	DISPLAY CONTROLLER, PALETTE DAC
Base Number Matches：	1

ICS5342VLF 数据手册

_DI_AC_TAS_S5_H3_E4_E2_T

GENDAC

ICS5342

16-Bit Integrated Clock-LUT-DAC

General Description

Features

The ICS5342 GENDAC is a combination of dual programma-

ble clock generators, a 256 x 18-bit RAM, and a triple 8-bit

video DAC. The GENDAC supports 8-bit pseudo color appli-

cations, as well as 15-bit, 16-bit, and 24-bit True Color bypass

for high speed, direct access to the DACs.

•

Triple video DAC, dual clock generator, and 16 bit pixel

port

Dynamic mode switch allows switching of color depth

on a pixel by pixel basis

24 (packed and sparse), 16, 15, or 8-bit pseudo color

pixel mode supports True Color, Hi-Color, and VGA

modes

The RAM makes it possible to display 256 colors selected

from a possible 262,144 colors. The dual clock generators use

Phase Locked Loop (PLL) technology to provide program-

mable frequencies for use in the graphics subsystem. The vid-

•

High speed 256 x 6 x 3 color palette (135 MHz) with

bypass mode and 8-bit DACs

eo clock contains

frequencies, all of which are

Eight programmable video (pixel) clock frequencies

(CLK0)

programmable by the user. The memory clock has two pro-

grammable frequency locations.

•

DAC power down in blanking mode

Anti-sparkle circuitry

The three 8-bit DACs on the ICS5342 are capable of driving

singly or doubly-terminated 75Ω loads to nominal 0 - 0.7

volts at pixel rates up to 135 MHz. Differential and integral

linearity errors are less than 1 LSB over full temperature and

VDD ranges. Monotonicity is guaranteed by design. On-chip

pixel mask register allows displayed colors to be changed in

a single write cycle rather than by modifying the color palette.

On-chip loop ﬁlters reduce external components

Standard CPU interface

Single external crystal (typically 14.318 MHz)

Monitor sense

Internal voltage reference

135 MHz (-3), 110 MHz (-2) & 80 MHz (-1) versions

Very low clock jitter

ICS is the world leader in all aspects of frequency (clock) gen-

eration for graphics, using patented techniques to produce

low jitter video timing.

Two latched frequency select pins or three non-latched

frequency select pins (programmable)

•

Hardware video checksum for manufacturing tests

Block Schematic

PCLK

COMPARE

SENSE*

BYPS

LATCH

P0-P15

BUFF.

RED

TRIPLE

6/8-BIT

DAC

GREEN

PIXEL

ADR

AND

BLUE

MUX

LATCH

COLOR

RSET

VREF

PALETTE

256 x 18

BIT

MASK

D0-D7

NORM

MICRO-

PROCESSOR

INTERFACE

WR*

RD*

TIMING

GEN.

MUX.

PCLK

RS0-RS2

STROBE

CS0-CS2

CTL

MODE

CLK0

BLANK*

8 PLL

PARAMETER &

CLK0 PLL

XIN

XTAL

OSC

1 PLL

CLK1

PARAMETER &

CLK1 PLL

XOUT

5342_01.ai

REV. 0.9.0

IDT™ / ICS™ 16-Bit Integrated Clock-LUT-DAC

ICS5342

12 3 4 5 6 7...35

中文翻译

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与ICS5342VLF相关器件

型号	品牌	获取价格	描述	数据表
ICS541	ICSI	获取价格	PRELIMINARY INFORMATION PLL Clock Divider
ICS541M	ICSI	获取价格	PRELIMINARY INFORMATION PLL Clock Divider
ICS541MT	ICSI	获取价格	PRELIMINARY INFORMATION PLL Clock Divider
ICS542	ICSI	获取价格	Clock Divider
ICS542	IDT	获取价格	CLOCK DIVIDER
ICS542M	ICSI	获取价格	Clock Divider
ICS542M	IDT	获取价格	Low Skew Clock Driver, 542 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.
ICS542MI	IDT	获取价格	Prescaler/Multivibrator
ICS542MILF	IDT	获取价格	CLOCK DIVIDER
ICS542MILFT	IDT	获取价格	Low Skew Clock Driver, 542 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.

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