Datasheet > iCE40HX1K-CB132

iCE40HX1K-CB132

更新时间： 2024-11-05 12:18:15

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
12页	872K
描述
iCE40â¢ HX-Series Ultra Low-Power FPGA Family

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iCE40HX1K-CB132 数据手册

iCE40^™HX-Series

Ultra Low-Power

FPGA Family

October 03, 2012 (1.32)

Data Sheet

Figure 1: iCE40 HX-Series Family Architectural Features

 HX-Series - optimized for high

Programmable

performance

Logic Block (PLB)

267 µA at f =0 kHz

 Low cost package offerings

 80% faster than iCE65

(Typical)

I/O Bank 0

 Proven, high-volume 40 nm, low-power

CMOS technology

Programmable Interconnect

 Integrated Phase-Locked Loop (PLL)

 Clock multiplication/division for display, SerDes,

and memory interface applications

 Up to 533 MHz PLL Output

 Reprogrammable from a variety of

methods and sources

 Flexible programmable logic and

programmable interconnect fabric

 8K look-up tables (LUT4) and flip-flops

 Low-power logic and interconnect

NVCM

PLL

 Complete iCEcube^™development system

 Windows^®and Linux^®support

SPI

I/O Bank 2

Config

 VHDL and Verilog logic synthesis

 Place and route software

Carry logic

Four-input

Look-Up Table

(LUT4)

Phase-Locked

Loop

Nonvolatile Configuration

Memory (NVCM)

Flip-flop with enable

and reset controls

 Design and IP core libraries

 Low-cost iCEman40HX development board

Table 1: iCE40HX Ultra Low-Power Programmable Logic Family Summary

Part Number

Logic Cells (LUT + Flip-Flop)

RAM4K Memory Blocks

HX1K

1,280

HX4K

3,520

HX8K

7,680

RAM4K RAM bits

64K

245 Kb

267 µA

80K

533 Kb

667 µA

107

128K

1,057 Kb

1100 µA

206

Phase-Locked Loops (PLLs)

Configuration bits (maximum)

Core Operating Power 0 KHz¹

Maximum Programmable I/O Pins

Maximum Differential Input Pairs

Package

Code Area mm Pitch mm

PIO: Max I/O (LVDS)

CM225

CB132

CT256

VQ100

TQ144

7x7

225-ball ucBGA

132-ball csBGA

256-ball caBGA

100-pin VQFP²

144-pin TQFP

0.4

0.5

0.8

0.5

178(23)

8x8

95(11)

95(12)

14x14

20x20

206(26)

72(9)

96(12)

107(14)

Note 1: At 1.2V VCC, 25°C 2: No PLL Available

www.latticesemi.com

(1.32, 03-OCT-2012)

12 3 4 5 6 7...12

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