iCE40™ HX-Series
Ultra Low-Power
mobileFPGA™ Family
March 30, 2012 (1.31)
Data Sheet
Figure 1: iCE40 HX-Series Family Architectural Features
HX-Series - Tablet targeted series
Programmable
optimized for high performance
Logic Block (PLB)
200 µA at f =0 kHz
Low cost package offerings
80% faster than iCE65
Tablet resolution HD video and imaging
(Typical)
I/O Bank 0
Programmable Interconnect
Proven, high-volume 40 nm, low-power
CMOS technology
Integrated Phase-Locked Loop (PLL)
Clock multiplication/division for display, SerDes,
and memory interface applications
Up to 533 MHz PLL Output
Reprogrammable from a variety of
methods and sources
Flexible programmable logic and
programmable interconnect fabric
NVCM
PLL
8K look-up tables (LUT4) and flip-flops
Low-power logic and interconnect
SPI
I/O Bank 2
Complete iCEcube™ development system
Windows® and Linux® support
Config
Carry logic
Four-input
Look-Up Table
(LUT4)
Phase-Locked
Loop
VHDL and Verilog logic synthesis
Place and route software
Nonvolatile Configuration
Memory (NVCM)
Flip-flop with enable
and reset controls
Design and IP core libraries
Low-cost iCEman40HX development board
Table 1: iCE40HX Ultra Low-Power Programmable Logic Family Summary
Part Number
Logic Cells (LUT + Flip-Flop)
RAM4K Memory Blocks
HX640
640
HX1K
1,280
16
HX4K
3,520
20
HX8K
7,680
32
8
RAM4K RAM bits
32K
1
120 Kb
200 µA
67
64K
1
245 Kb
267 µA
95
80K
2
533 Kb
667 µA
95
128K
2
1,057 Kb
1100 µA
206
Phase-Locked Loops (PLLs)
Configuration bits (maximum)
Core Operating Power 0 KHz1
Maximum Programmable I/O Pins
Maximum Differential Input Pairs
8
11
12
26
Package
225-ball BGA
132-ball BGA
284-ball BGA
256-ball BGA
Code Area mm Pitch mm Programmable I/O: Max I/O (LVDS)
CM225
CB132
CB284
CT256
VQ100
7x7
0.4
0.5
0.5
0.8
0.5
178(23)
8x8
95(11)
72(9)
95(12)
95(12)
12x12
14x14
14x14
206(26)
67(8)
100-pin quad flat pack
Note 1: At 1.2V VCC
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www.latticesemi.com
(1.31, 30-MAR-2012)
1