Discontinued (9/98 - last order; 3/99 last ship)
IBM11M4730C4M
x 72 E12/10, 5.0V, Au.
IBM11N4645BB IBM11N4735BB
IBM11N4645CB IBM11N4735CB
4M x 64/72 DRAM Module
Features
• 168 Pin JEDEC Standard, Unbuffered 8 Byte
Dual In-line Memory Module
• System Performance Benefits:
-Non buffered for increased performance
• 4Mx64, 4Mx72 Extended Data Out Page Mode
DIMMS
-Reduced noise (35 V /V pins)
SS CC
-Byte write, byte read accesses
-Serial PDs
• Performance:
-50
-60
• Extended Data Out (EDO) Mode, Read-Modify-
Write Cycles
tRAC
tCAC
tAA
RAS Access Time
CAS Access Time
50ns
13ns
60ns
15ns
30ns
• Refresh Modes: RAS-Only, CBR and Hidden
Refresh
Access Time From Address 25ns
tRC
Cycle Time
84ns 104ns
20ns 25ns
tHPC
EDO Mode Cycle Time
• 2048 refresh cycles distributed across 32ms
(11/11 addressing)
• Inputs and outputs are LVTTL (3.3V) compatible
• 4096 refresh cycles distributed across 64ms
(12/10 addressing)
• Single 3.3V ± 0.3V Power Supply
• Au contacts
• 11/11 or 12/10 addressing (Row/Column)
• Card size: 5.25" x 1.0" x 0.354"
• DRAMS in SOJ Package
• Optimized for byte-write non-parity, or ECC
applications
Description
IBM11N4645BB/IBM11N4645CB are industry stan-
dard 168-pin 8-byte Dual In-line Memory Modules
(DIMMs) which are organized as 4Mx64 and 4Mx72
high speed memory arrays designed with EDO
DRAMs for non-parity or ECC applications. The
DIMMs use 16 (x64) or 18 (x72) 4Mx4 EDO DRAMs
in SOJ packages. The use of EDO DRAMs allows
for a reduction in Page Mode Cycle time from 40ns
(Fast Page) to 20ns for 50ns DRAM modules.
clock data between the master (system logic) and
the slave EEPROM device (DIMM). The EEPROM
device address pins (SA0-2) are brought out to the
DIMM tabs to allow 8 unique DIMM/EEPROM
addresses. The first 128 bytes are utilized by the
DIMM manufacturer and the second 128 bytes of
serial PD data are available to the customer.
All IBM 168-pin DIMMs provide a high performance,
flexible 8-byte interface in a 5.25” long space-saving
footprint. Related products include the buffered
DIMMs (x64 non- parity and x72 ECC Optmized) for
applications which can benefit from the on-card buff-
ers.
The DIMMs use serial presence detects imple-
mented via a serial EEPROM using the two pin I C
2
protocol. This communication protocol uses Clock
(SCL) and Data I/O (SDA) lines to synchronously
Card Outline
(Front)
(Back)
1
85
10 11
94 95
84
168
40 41
124 125
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H8036.E22441E
Revised 5/98
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