Datasheet > IBM0418A41NLAB-3

IBM0418A41NLAB-3

更新时间： 2023-01-03 08:22:09

品牌	Logo	应用领域
国际商业机器公司 - IBM		静态存储器
页数	文件大小	规格书
25页	477K
描述
Standard SRAM, 256KX18, 1.8ns, CMOS, PBGA119, BGA-119

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技术参数
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IBM0418A41NLAB-3 技术参数

生命周期：	Contact Manufacturer	零件包装代码：	BGA
包装说明：	BGA, BGA119,7X17,50	针数：	119
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.51
最长访问时间：	2 ns	其他特性：	LATE WRITE
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B119
长度：	22 mm	内存密度：	4718592 bit
内存集成电路类型：	STANDARD SRAM	内存宽度：	18
功能数量：	1	端子数量：	119
字数：	262144 words	字数代码：	256000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：		组织：	256KX18
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA119,7X17,50
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY
并行/串行：	PARALLEL	电源：	2.5,3.3 V
认证状态：	Not Qualified	座面最大高度：	2.679 mm
最大待机电流：	0.1 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.415 mA
最大供电电压 (Vsup)：	3.63 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	宽度：	14 mm
Base Number Matches：	1

IBM0418A41NLAB-3 数据手册

IBM0436A41NLAB IBM0418A41NLAB

IBM0418A81NLAB IBM0436A81NLAB

8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM

SRAM Features

Late Write

The late write function allows for write data to be registered one cycle after addresses and controls. This fea-

ture eliminates one bus-turnaround cycle, necessary when going from a read to a write operation. Late write

is accomplished by buffering write addresses and data so that the write operation occurs during the next write

cycle. When a read cycle occurs after a write cycle, the address and write data information are stored tempo-

rarily in holding registers. During the first write cycle preceded by a read cycle, the SRAM array will be

updated with address and data from the holding registers. Read cycle addresses are monitored to determine

if read data is to be supplied from the SRAM array or the write buffer. The bypassing of the SRAM array

occurs on a byte-by-byte basis. When only one byte is written during a write cycle, read data from the last

written address will have new byte data from the write buffer and remaining bytes from the SRAM array.

Mode Control

Mode control pins M1 and M2 are used to select four different JEDEC-standard read protocols. This SRAM

supports a single clock pipeline (M1 = V , M2 = V ). This datasheet only describes single-clock pipeline

functionality. Mode control inputs must be set on power up and must not change during SRAM operation.

This SRAM is tested only in the pipeline mode.

Sleep Mode

Sleep mode is enabled by switching synchronous signal ZZ high. When the SRAM is in sleep mode, the out-

puts will go to a High-Z state and the SRAM will draw standby current. SRAM data will be preserved and a

recovery time (t

) is required before the SRAM resumes normal operation.

ZZR

Power-Up Requirements

In order to guarantee the optimum internally regulated supply voltage, the SRAM requires 4µs of power-up

time after V reaches its operating range.

Power-Up and Power-Down Sequencing

The power supplies need to be powered up in the following order: V , V

, and inputs. The power-down

DDQ

sequencing must be in the reverse order. V

can be allowed to exceed V by no more than 0.6V.

DDQ

crrL3325.06.fm

June 13, 2002

Page 6 of 25

1...3 4 567 8 9...25

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与IBM0418A41NLAB-3相关器件

型号	品牌	获取价格	描述	数据表
IBM0418A41NLAB-3N	IBM	获取价格	Standard SRAM, 256KX18, 2ns, CMOS, PBGA119, BGA-119
IBM0418A41QLAA-3	ETC	获取价格	x18 Fast Synchronous SRAM
IBM0418A41QLAA-3N	ETC	获取价格	x18 Fast Synchronous SRAM
IBM0418A41QLAA-4	ETC	获取价格	x18 Fast Synchronous SRAM
IBM0418A41QLAA-5	ETC	获取价格	x18 Fast Synchronous SRAM
IBM0418A41QLAB-3	IBM	获取价格	Standard SRAM, 256KX18, 1.7ns, CMOS, PBGA119, BGA-119
IBM0418A41QLAB-3F	IBM	获取价格	Standard SRAM, 256KX18, 1.8ns, CMOS, PBGA119, BGA-119
IBM0418A41QLAB-3N	IBM	获取价格	Standard SRAM, 256KX18, 1.8ns, CMOS, PBGA119, BGA-119
IBM0418A41QLAB-3P	IBM	获取价格	Standard SRAM, 256KX18, 1.5ns, CMOS, PBGA119, BGA-119
IBM0418A41QLAB-4	IBM	获取价格	Standard SRAM, 256KX18, 2ns, CMOS, PBGA119, BGA-119

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