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IBM04184ARLAD-6F PDF预览

IBM04184ARLAD-6F

更新时间: 2024-01-19 02:58:54
品牌 Logo 应用领域
国际商业机器公司 - IBM 静态存储器内存集成电路
页数 文件大小 规格书
22页 159K
描述
Standard SRAM, 256KX18, 6.5ns, CMOS, PBGA119, BGA-119

IBM04184ARLAD-6F 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Lifetime Buy零件包装代码:BGA
包装说明:BGA, BGA119,7X17,50针数:119
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.55
最长访问时间:6.5 nsI/O 类型:COMMON
JESD-30 代码:R-PBGA-B119JESD-609代码:e0
长度:22 mm内存密度:4718592 bit
内存集成电路类型:STANDARD SRAM内存宽度:18
功能数量:1端子数量:119
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:组织:256KX18
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA119,7X17,50
封装形状:RECTANGULAR封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:2.5,3.3 V认证状态:Not Qualified
座面最大高度:2.679 mm最大待机电流:0.12 A
最小待机电流:3.14 V子类别:SRAMs
最大压摆率:0.45 mA最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

IBM04184ARLAD-6F 数据手册

 浏览型号IBM04184ARLAD-6F的Datasheet PDF文件第2页浏览型号IBM04184ARLAD-6F的Datasheet PDF文件第3页浏览型号IBM04184ARLAD-6F的Datasheet PDF文件第4页浏览型号IBM04184ARLAD-6F的Datasheet PDF文件第5页浏览型号IBM04184ARLAD-6F的Datasheet PDF文件第6页浏览型号IBM04184ARLAD-6F的Datasheet PDF文件第7页 
.
IBM04184ARLAD  
IBM04364ARLAD  
Preliminary  
Features  
128K x 36 & 256K x 18 SRAM  
• Registered Addresses, Write Enables, Synchro-  
nous Select and Data Ins  
• 128K x 36 or 256K x 18 Organizations  
CMOS Technology  
• Latched Outputs  
• Synchronous Register-Latch Mode Of Opera-  
tion with Self-Timed Late Write  
• Asynchronous Output Enable and Power Down  
Inputs  
• Single Differential PECL Clock compatible with  
LVTTL Levels  
• Boundary Scan using limited set of JTAG  
1149.1 functions  
+3.3V Power Supply, V  
& Ground  
DDQ  
• Byte Write Capability & Global Write Enable  
• Common I/O & LVTTL I/O Compatible  
• 7 x 17 Bump Ball Grid Array Package with  
SRAM JEDEC Standard Pinout and Boundary  
SCAN Order.  
Description  
The IBM04184ARLAD and IBM04364ARLAD 4Mb  
SRAMS are Synchronous Register-Latch Mode,  
high performance CMOS Static Random Access  
Memories that are versatile, wide I/O, and achieve  
6ns cycle and 5.5ns access times. Dual differential  
K clocks are used to initiate the read/write operation  
and all internal operations are self-timed. At the ris-  
ing edge of the K Clock, all Addresses, Write-  
Enables, Sync Select, and Data Ins are registered  
internally. Data Outs are updated from output  
latches off the falling edge of the K Clock. An inter-  
nal Write buffer allows write data to follow one cycle  
after addresses and controls. The chip is operated  
with a +3.3V power supply, has a 2.5V or 3.3V Out-  
put Power Supply, and is compatible with LVTTL I/O  
interfaces.  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
75H4338  
Revised 2/99  
Page 1 of 22  

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